Microprocessors and Microsystems
 2013
DOI: 10.1016/j.micpro.2013.08.007
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Performance effects of pipeline architecture on an FPGA-based binary32 floating point multiplier

Xianyang Jiang
1
,
Peng Xiao
2
,
Meikang Qiu
3
et al.
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Cited by 8 publications
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