Performance Enhancement of Conventional Design of 4-Bit Carry Look-Ahead Adder

Joy, Upal Barua; Chakraborty, Avishek; Sen, Swagata; Das, Arka; Biswas, Preyonti; Tasnim, Afra

doi:10.1109/icrest57604.2023.10070089

Cited by 1 publication

(1 citation statement)

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“…Joy, Chakraborty [26] presented a novel design for a Hybrid 4-bit Carry Look-Ahead (CLA) adder that utilizes gate diffusion input and scaled complementary metal-Oxide-semiconductor (S-CMOS) logic. The design suggestion exhibited a noteworthy mean power enhancement and a more significant delay improvement.…”

Section: Literature Reviewmentioning

confidence: 99%

A new nano-design of 16-bit carry look-ahead adder based on quantum technology

Ahmadpour,

Jafari Navimipour

2023

Phys. Scr.

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There is a requirement and a desire to develop reliable and energy-efficient circuit designs that adapt to the expanding field of low-power circuit engineering in the VLSI domain based on nanotechnology. The quantum-dot cellular automata (QCA) technology possesses the potential to supplant the conventional, complementary metal-oxide-semiconductor (CMOS) technology in low-power nano-scale applications due to its diminutive cell dimensions, dependable circuitry architecture, and robust structural integrity. On the other hand, the carry look-ahead adder (CLA) is one of the vital circuits in digital processing utilized in diverse digital applications. In addition, for the design of this essential circuit, the occupied area and the delay play the primary role because using a simple formulation can reduce the occupied area, energy consumption, and the number of gates count. In the previous structures, high delay and use of traditional technology (like CMOS) caused an increase in the number of gate counts and occupied areas. Using QCA technology, simple quantum cells, and a low delay, all the previous shortcomings can be resolved to reduce the number of gate counts and low occupied area in the CLA circuit. This paper proposes a new method that helps the propagation characteristics generate suitable signals to reduce the number of gate counts based on adders in QCA technology. Several new blocks are used to design fast binary adders. Finally, an optimal four and 16-bit CLA circuit will be proposed based on the adder circuit. Furthermore, the execution and experimentation of outcomes are carried out utilizing QCADesigner-2.0.3. The simulation-based comparison of values justified the proposed design’s accuracy and efficiency. The simulation results demonstrate that the proposed circuit has a low area and quantum cell.

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Section: Literature Reviewmentioning

confidence: 99%