Performance Enhancement of STT MRAM Using Asymmetric- Sidewall-Spacer NMOS

Abstract

Conventional spin transfer torque (STT) magnetoresistive random access memory (MRAM) generally includes a bulk n-channel MOS (NMOS) transistor as an access device that provides equal drive current in standalone conditions in both the directions. However, the switching current requirement of magnetic tunnel junctions (MTJs) in STT MRAM is highly asymmetric (2 to 3:1). With conventional access devices, the excess write current in one direction maps to unnecessarily higher power dissipation. Hence, in this paper, a novel STT MRAM cell with an asymmetric-dielectric (asymmetric-k) sidewall-spacer NMOS (ASNMOS) is presented. ASNMOS has different-k sidewall spacers, i.e., one side high-k and other side low-k spacer. As desired, this novel ASNMOS provides asymmetric drive current and reduces the overall power dissipation. The proposed STT MRAM cell is analyzed with HSPICE simulations using calibrated Verilog-A models for access device and perpendicular magnetic anisotropy MTJ. The STT MRAM cell with the proposed ASNMOS exhibits up to 25% reduction in the dynamic power dissipation over the STT MRAM cell with the conventional symmetric NMOS as an access device. Moreover, ASNMOS-based cells shows higher reliability wherein the worst case current density through MTJ is reduced by 25%. IndexTerms-Asymmetric-k sidewall-spacer NMOS (ASNMOS), HfO 2 spacer, magneto-resistive random access memory (MRAM), spin transfer torque (STT), write margin (WM).