Performance Enhancements in Scaled Strained-SiGe pMOSFETs With $ \hbox{HfSiO}_{x}/\hbox{TiSiN}$ Gate Stacks

Alatise, Olayiwola; Olsen, SH; Cowern, N.E.B.; O'Neill, AG; Majhi, P.

doi:10.1109/ted.2009.2028375

Cited by 4 publications

(4 citation statements)

References 41 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…4), stems from the lower effective mass of Ge as compared to Si. However, this mobility gain is higher than previously demonstrated in the literature [13,14]. The effective gate length impact can be neglected in long devices as L = 10 lm.…”

Section: Room Temperature Measurementsmentioning

confidence: 57%

Unexpected impact of germanium content in SiGe bulk PMOSFETs

Diouf¹,

Cros²,

Soussou³

et al. 2013

Solid-State Electronics

View full text Add to dashboard Cite

Section: Room Temperature Measurementsmentioning

confidence: 57%

Unexpected impact of germanium content in SiGe bulk PMOSFETs

Diouf¹,

Cros²,

Soussou³

et al. 2013

Solid-State Electronics

View full text Add to dashboard Cite

“…Many studies have reported that strain is unequally distributed along the channel induced by a uniaxial or biaxial stressor [1]- [6]. The electrical properties related to strain structure have also been reported to be channel length dependent [8]- [12], [16]- [20]. However, only a few studies have focused on the relationship between channel width and length in terms of comparing the impacts of unstrained and strained devices, particularly with decreasing size.…”

Section: Introductionmentioning

confidence: 99%

“…Alatise et al [20] have reported that drain current is enhanced in strained SiGe p-MOSFETs when the gate channel is 1 μm, but is degraded when the gate channel is 100 nm. However, the relationship of channel orientation to channel dimension has not been considered in their study.…”

Section: Introductionmentioning

confidence: 99%

Performance Dependence on Width-to-Length Ratio of Si Cap/SiGe Channel MOSFETs

Chang

Lin

2013

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

This paper measures the n-and p-MOSFETs fabricated through 65-nm high-k/metal gate CMOSFET process flow. The [110] channels of the Si cap on SiGe with different width (W ) and length (L) ratios were compared with Si-only channels. The results show that a high W-L ratio in the [110] n-channel can alleviate the degradation of biaxial compressive stress. Meanwhile, a low W-L ratio in the p-channel can improve the performance; however, the ratio should at least be below two in this paper. The dominance of the longitudinal or transverse configurations successfully explains this phenomenon because of the reliance of the different levels of piezoresistance coefficient on the channel orientation. The threshold voltage shifts versus the W-L ratio in the p-channel is in agreement with the result. The result is verified by a quantitative current comparison at a high bias in the n-/p-channels between the strained SiGe and Si-only channels, which shows that an extreme W-L ratio in the original biaxially strained SiGe channel can result in longitudinal or transverse strain, thereby leading to different levels of performance degradation/improvement.

show abstract

“…performed. Details of the fabrication process are given elsewhere [7]. Si control pMOSFETs were co-fabricated under the same processing conditions.…”

Section: Introductionmentioning

confidence: 99%