Performance Estimation for Exascale Reconfigurable Dataflow Platforms

Yasudo, Ryota; Coutinho, J.G.F.; Vărbănescu, Ana Lucia; Luk, Wayne; Amano, Hideharu; Becker, Tobias

doi:10.1109/fpt.2018.00062

Cited by 8 publications

(9 citation statements)

References 13 publications

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“…Therefore, this approach is infeasible in general, as it is usually constrained to a single hardware configuration. Nevertheless, there have been a few researchers who have proposed general performance estimation methodologies [12][13][14].…”

Section: Performance Estimationmentioning

confidence: 99%

“…A performance estimation framework for reconfigurable dataflow platforms was proposed by Yasudo et al [12], which can analytically determine the number of accelerator units suitable for an application. Dai et al [13] proposed an estimation method based on a GTB and a high-level synthesis report.…”

Section: Performance Estimationmentioning

confidence: 99%

“…There are several performance estimation frameworks for reconfigurable accelerators [12][13][14]; however, estimating the performance without knowing the run-time intricacies when running different NNs is still a challenging task. There are two main reasons for this complication: (1) the cost of executing a certain operation on hardware varies by on/offchip communication, synchronisation, control signals, I/O interruptions, in particular for the NN accelerators, the NN's architecture, complicating the estimation; (2) it is difficult to accurately select the most representative design features for all hardware specifications during performance estimation.…”

Section: Introductionmentioning

confidence: 99%

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Improving Performance Estimation for Design Space Exploration for Convolutional Neural Network Accelerators

et al. 2021

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Contemporary advances in neural networks (NNs) have demonstrated their potential in different applications such as in image classification, object detection or natural language processing. In particular, reconfigurable accelerators have been widely used for the acceleration of NNs due to their reconfigurability and efficiency in specific application instances. To determine the configuration of the accelerator, it is necessary to conduct design space exploration to optimize the performance. However, the process of design space exploration is time consuming because of the slow performance evaluation for different configurations. Therefore, there is a demand for an accurate and fast performance prediction method to speed up design space exploration. This work introduces a novel method for fast and accurate estimation of different metrics that are of importance when performing design space exploration. The method is based on a Gaussian process regression model parametrised by the features of the accelerator and the target NN to be accelerated. We evaluate the proposed method together with other popular machine learning based methods in estimating the latency and energy consumption of our implemented accelerator on two different hardware platforms targeting convolutional neural networks. We demonstrate improvements in estimation accuracy, without the need for significant implementation effort or tuning.

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Section: Performance Estimationmentioning

confidence: 99%

Section: Performance Estimationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Improving Performance Estimation for Design Space Exploration for Convolutional Neural Network Accelerators

et al. 2021

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“…As with profiling, we employ a generic technique to generate models for arbitrary functions, treating implementations as black boxes. This approach enables model generation for implementations without requiring source code access, whereas many other performance modelling techniques require such access to extract application features [19] [8] [18] [9]. Sample Cleaning.…”

Section: Model Generationmentioning

confidence: 99%

Scheduling Hardware-Accelerated Cloud Functions

Vandebon

Coutinho

Luk

2021

J Sign Process Syst

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This paper presents a Function-as-a-Service (FaaS) approach for deploying managed cloud functions onto heterogeneous cloud infrastructures. Current FaaS systems, such as AWS Lambda, allow domain-specific functionality, such as AI, HPC and image processing, to be deployed in the cloud while abstracting users from infrastructure and platform concerns. Existing approaches, however, use a single type of resource configuration to execute all function requests. In this paper, we present a novel FaaS approach that allows cloud functions to be effectively executed across heterogeneous compute resources, including hardware accelerators such as GPUs and FPGAs. We implement heterogeneous scheduling to tailor resource selection to each request, taking into account performance and cost concerns. In this way, our approach makes use of different processor types and quantities (e.g. 2 CPU cores), uniquely suited to handle different types of workload, potentially providing improved performance at a reduced cost. We validate our approach in three application domains: machine learning, bio-informatics, and physics, and target a hardware platform with a combined computational capacity of 24 FPGAs and 12 CPU cores. Compared to traditional FaaS, our approach achieves a cost improvement for non-uniform traffic of up to 8.9 times, while maintaining performance objectives.

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“…There are several performance estimation frameworks for reconfigurable FP-GA-based accelerators [19,2,3], however, estimating the performance without knowing about scheduling is still a very challenging task because of two main reasons. First, the explicit time to execute a certain operation on hardware varies by on/off-chip communication, synchronisation, control signals, I/O interruptions and in particular for the CNN accelerators -the CNN's architecture, which complicate analytic estimation.…”

Section: Introductionmentioning

confidence: 99%

Improving Performance Estimation for FPGA-Based Accelerators for Convolutional Neural Networks

Ferianc

Fan

Chu

et al. 2020

Lecture Notes in Computer Science

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Field-programmable gate array (FPGA) based accelerators are being widely used for acceleration of convolutional neural networks (CNNs) due to their potential in improving the performance and reconfigurability for specific application instances. To determine the optimal configuration of an FPGA-based accelerator, it is necessary to explore the design space and an accurate performance prediction plays an important role during the exploration. This work introduces a novel method for fast and accurate estimation of latency based on a Gaussian process parametrised by an analytic approximation and coupled with runtime data. The experiments conducted on three different CNNs on an FPGAbased accelerator on Intel Arria 10 GX 1150 demonstrated a 30.7% improvement in accuracy with respect to the mean absolute error in comparison to a standard analytic method in leave-one-out cross-validation.

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Performance Estimation for Exascale Reconfigurable Dataflow Platforms

Cited by 8 publications

References 13 publications

Improving Performance Estimation for Design Space Exploration for Convolutional Neural Network Accelerators

Improving Performance Estimation for Design Space Exploration for Convolutional Neural Network Accelerators

Scheduling Hardware-Accelerated Cloud Functions

Improving Performance Estimation for FPGA-Based Accelerators for Convolutional Neural Networks

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