Performance evaluation and implementations of MFCC, SVM and MLP algorithms in the FPGA board

Abstract

One of the most difficult speech recognition tasks is accurate recognition of human-to-human communication. Advances in deep learning over the last few years have produced major speech improvements in recognition on the representative Switch-board conversational corpus. Word error rates that just a few years ago were 14% have dropped to 8.0%, then 6.6% and most recently 5.8%, and are now believed to be within striking range of human performance. This raises two issues - what is human performance, and how far down can we still drive speech recognition error rates? The main objective of this article is the development of a comparative study of the performance of Automatic Speech Recognition (ASR) algorithms using a database made up of a set of signals created by female and male speakers of different ages. We will also develop techniques for the Software and Hardware implementation of these algorithms and test them in an embedded electronic card based on a reconfigurable circuit (Field Programmable Gate Array FPGA). We will present an analysis of the results of classifications for the best Support Vector Machine architectures (SVM) and Artificial Neural Networks of Multi-Layer Perceptron (MLP). Following our analysis, we created NIOSII processors and we tested their operations as well as their characteristics. The characteristics of each processor are specified in this article (cost, size, speed, power consumption and complexity). At the end of this work, we physically implemented the architecture of the Mel Frequency Cepstral Coefficients (MFCC) extraction algorithm as well as the classification algorithm that provided the best results.

Use Brain-Like Audio Features to Improve Speech Recognition Performance

“…CNNs and recurrent neural networks (RNNs) are widely used for speech recognition. CNNs can efficiently analyze and process input spectrograms and are suitable for processing spatial features, while RNNs can efficiently analyze time series data and are suitable for processing temporal features [11]. Therefore, the combination of these two methods is advantageous.…”

Implementation on <i>FPGA</i> of Neuro-Genetic PID Controllers Auto-Tuning

“…This work uses the MPGA with NN to support the PID autotuning using the soft-processor NIOS II inside an FPGA board as a platform. This approach presents the advantage of the possibility of the designer of embedded systems defining a specific core inside the NIOS II for her/his specific needs [19]. The low power consumption when we use an FPGA board [20] compared to the PC power is indubitably another advantage.…”