Performance evaluation and prediction for parallel algorithms on the BBN GP1000

Bodin, François; Windheiser, Daniel; Jalby, William; Atapattu, Daya; Lee, Mann-Ho; Gannon, Dennis

doi:10.1145/255129.255182

Cited by 15 publications

(5 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…If we neglect the interaction between channels and assume that all internal buses are utilizable by all channels and PEs, then we have the following analytic model developed on top of the previous parallelizing theorem [2,12]: …”

Section: Discussionmentioning

confidence: 99%

Power-Aware Scheduling for Parallel Security Processors with Analytical Models

Lin

You

Huang

et al. 2005

Lecture Notes in Computer Science

View full text Add to dashboard Cite

Abstract. Techniques to reduce power dissipation for embedded systems have recently come into sharp focus in the technology development. Among these techniques, dynamic voltage scaling (DVS), power gating (PG), and multipledomain partitioning are regarded as effective schemes to reduce dynamic and static power. In this paper, we investigate the problem of power-aware scheduling tasks running on a scalable encryption processor, which is equipped with heterogeneous distributed SOC designs and needs the effective integration of the elements of DVS, PG, and the scheduling for correlations of multiple domain resources. We propose a novel heuristic that integrates the utilization of DVS and PG and increases the total energy-saving. Furthermore, we propose an analytic model approach to make an estimate about its performance and energy requirements between different components in systems. These proposed techniques are essential and needed to perform DVS and PG on multiple domain resources which are of correlations. Experiments are done in the prototypical environments for our security processors and the results show that significant energy reductions can be achieved by incorporating our algorithms. 12

show abstract

Section: Discussionmentioning

confidence: 99%

Power-Aware Scheduling for Parallel Security Processors with Analytical Models

Lin

You

Huang

et al. 2005

Lecture Notes in Computer Science

View full text Add to dashboard Cite

show abstract

“…Kisuki et al implement a compiler that traverses the optimization space for loop unrolling and tiling and runs all the produced code to choose the best version of a loop kernel [6]. Bodin et al propose an iterative compilation technique that balances code size and performance [19]. These approaches have large compile times because they search a prohibitively large optimization space and they involve running each version of the program in order to gauge its performance.…”

Section: The Promise Of Iterative Compilationmentioning

confidence: 99%

Compiler optimization-space exploration

Triantafyllis

Vachharajani

August³

International Symposium on Code Generation and Optimization, 2003. CGO 2003.

128

171

View full text Add to dashboard Cite

To meet the demands of modern architectures, optimizing compilers must incorporate an ever larger number of increasingly complex transformation algorithms. Since code transformations may often degrade performance or interfere with subsequent transformations, compilers employ predictive heuristics to guide optimizations by predicting their effects a priori. Unfortunately, the unpredictability of optimization interaction and the irregularity of today's wide-issue machines severely limit the accuracy of these heuristics. As a result, compiler writers may temper high variance optimizations with overly conservative heuristics or may exclude these optimizations entirely. While this process results in a compiler capable of generating good average code quality across the target benchmark set, it is at the cost of missed optimization opportunities in individual code segments.To replace predictive heuristics, researchers have proposed compilers which explore many optimization options, selecting the best one a posteriori. Unfortunately, these existing iterative compilation techniques are not practical for reasons of compile time and applicability. In this paper, we present the Optimization-Space Exploration (OSE) compiler organization, the first practical iterative compilation strategy applicable to optimizations in general-purpose compilers. Instead of replacing predictive heuristics, OSE uses the compiler writer's knowledge encoded in the heuristics to select a small number of promising optimization alternatives for a given code segment. Compile time is limited by evaluating only these alternatives for hot code segments using a general compiletime performance estimator. An OSE-enhanced version of Intel's highly-tuned, aggressively optimizing production compiler for IA-64 yields a significant performance improvement, more than 20% in some cases, on Itanium for SPEC codes.

show abstract

“…If we neglect the interaction between channels and assume that all internal buses are utilizable by all channels and PEs, we have the following analytic model developed on top of a previous parallelizing theorem [44,45]:…”

Section: Appendix 2 Analytical Modelsmentioning

confidence: 99%

Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains

et al. 2007

View full text Add to dashboard Cite

Dynamic voltage scaling (DVS) and power gating (PG) have become mainstream technologies for low-power optimization in recent years. One issue that remains to be solved is integrating these techniques in correlated domains operating with multiple voltages. This article addresses the problem of power-aware task scheduling on a scalable cryptographic processor that is designed as a heterogeneous and distributed system-on-a-chip, with the aim of effectively integrating DVS, PG, and the scheduling of resources in multiple voltage domains (MVD) to achieve low energy consumption. Our approach uses an analytic model as the basis for estimating the performance and energy requirements between different domains and addressing the scheduling issues for correlated resources in systems. We also present the results of performance and energy simulations from transaction-level models of our security processors in a variety of system configurations. The prototype experiments show that our proposed methods yield significant energy reductions. The proposed techniques will be useful for implementing DVS and PG in domains with multiple correlated resources.

show abstract

Performance evaluation and prediction for parallel algorithms on the BBN GP1000

Cited by 15 publications

References 1 publication

Power-Aware Scheduling for Parallel Security Processors with Analytical Models

Power-Aware Scheduling for Parallel Security Processors with Analytical Models

Compiler optimization-space exploration

Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains

Contact Info

Product

Resources

About