Performance evaluation for a compressed-VLIW processor

Jee, Sung-Hyun; Palaniappan, Kannappan

doi:10.1145/508791.508967

Cited by 9 publications

(3 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Existing NOP compression techniques [Conte et al 1996;Jee and Palaniappan 2002] are irrelevant to the instruction bus width reduction. They also focus only on the code size reduction.…”

Section: Related Workmentioning

confidence: 99%

Reducing instruction bit-width for low-power VLIW architectures

Lee

Youn

Cho

et al. 2013

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

VLIW (very long instruction word) architectures have proven to be useful for embedded applications with abundant instruction level parallelism. But due to the long instruction bus width it often consumes more power and memory space than necessary. One way to lessen this problem is to adopt a reduced bit-width instruction set architecture (ISA) that has a narrower instruction word length. This facilitates a more efficient hardware implementation in terms of area and power by decreasing bus-bandwidth requirements and the power dissipation associated with instruction fetches. In practice, however, it is impossible to convert a given ISA fully into an equivalent reduced bit-width one because the narrow instruction word, due to bitwidth restrictions, can encode only a small subset of normal instructions in the original ISA. Consequently, existing processors provide narrow instructions in very limited cases along with severe restrictions on register accessibility. The objective of this work is to explore the possibility of complete conversion, as a case study, of an existing 32-bit VLIW ISA into a 16-bit one that supports effectively all 32-bit instructions. To this objective, we attempt to circumvent the bit-width restrictions by dynamically extending the effective instruction word length of the converted 16-bit operations. Further, we will show that our proposed ISA conversion can create a synergy effect with a VLES (variable length execution set) architecture that is adopted in most recent VLIW processors. According to our experiment, the code size becomes significantly smaller after the conversion to 16-bit VLIW code. Also at a slight run time cost, the machine with the 16-bit ISA consumes much less energy than the original machine.

show abstract

“…Existing NOP compression techniques [Conte et al 1996;Jee and Palaniappan 2002] are irrelevant to the instruction bus width reduction. They also focus only on the code size reduction.…”

Section: Related Workmentioning

confidence: 99%

Reducing instruction bit-width for low-power VLIW architectures

Lee

Youn

Cho

et al. 2013

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

show abstract

“…In [7] and [8], the authors use a mask word that encodes which operations are present in the following bundle. • Instruction template bits.…”

Section: Related Workmentioning

confidence: 99%

A sparse VLIW instruction encoding scheme compatible with generic binaries

Brandon

Hoozemans

Straten

et al. 2015

2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

View full text Add to dashboard Cite

Very Long Instruction Word (VLIW) processors are commonplace in embedded systems due to their inherent lowpower consumption as the instruction scheduling is performed by the compiler instead by sophisticated and power-hungry hardware instruction schedulers used in their RISC counterparts. This is achieved by maximizing resource utilization by only targeting a certain application domain. However, when the inherent application ILP (instruction-level parallelism) is low, resources are under-utilized/wasted and the encoding of NOPs results in large code sizes and consequently additional pressure on the memory subsystem to store these NOPs.To address the resource-utilization issue, we proposed a dynamic VLIW processor design that can merge unused resources to form additional cores to execute more threads. Therefore, the formation of cores can result in issue widths of 2, 4, and 8. Without sacrificing the possibility of code interruptability and resumption, we proposed a generic binary scheme that allows a single binary to be executed on these different issue-width cores. However, the code size issue remains as the generic binary scheme even slightly further increases the number NOPS. Therefore, in this paper, we propose to apply a well-known stop-bit code compression technique to the generic binaries that, most importantly, maintains its code compatibility characteristic allowing it to be executed on different cores. In addition, we present the hardware designs to support this technique in our dynamic core. For prototyping purposes, we implemented our design on a Xilinx Virtex-6 FPGA device and executed 14 embedded benchmarks. For comparison, we selected a nondynamic/static VLIW core that incorporates a similar stop-bit technique for its code compression.We demonstrate, while maintaining code compatibility on top of a flexible dynamic VLIW processor, that the code size can be significantly reduced (up to 80%) resulting in energy savings, and that the performance can be increased (up to a factor of three). Finally, our experimental results show that we can use smaller caches (2 to 4 times as small), which will further help in decreasing energy consumption.

show abstract

“…The approach in [7] eliminates many NOP operations by encoding only data dependencies and enabling different execution slots to execute operations from different instruction words. This however requires considerable changes to the processor architecture and adds complexity to the processor's control logic.…”

Section: Related Workmentioning

confidence: 99%

Compiler optimizations for code density of variable length instructions

Kultala

Viitanen

Jääskeläinen

et al. 2014

2014 IEEE Workshop on Signal Processing Systems (SiPS)

View full text Add to dashboard Cite

Variable length encoding can considerably decrease code size in VLIW processors by decreasing the amount of bits wasted on encoding No Operation(NOP)s. A processor may have different instruction templates where different execution slots are implicitly NOPs, but all combinations of NOPs may not be supported by the instruction templates. The efficiency of the NOP encoding can be improved by the compiler trying to place NOPs in such way that the usage of implicit NOPs is maximized. Two different methods of optimizing the use of the implicit NOP slots are evaluated: prioritizing function units that have fewer implicit NOPs associated to them, and a post-pass to the instruction scheduler which utilizes the slack of the schedule by rescheduling operations with slack into different instruction words so that the available instruction templates are better utilized. The postpass optimizer saved an average of 2.5 % and at best of 9.1 % instruction memory, without performance loss. Prioritizing function units gave best case instruction memory savings of 12.7 % but the average savings were only 1.0 % and there was in average 5.7 % slowdown for the program.

show abstract

Performance evaluation for a compressed-VLIW processor

Cited by 9 publications

References 4 publications

Reducing instruction bit-width for low-power VLIW architectures

Reducing instruction bit-width for low-power VLIW architectures

A sparse VLIW instruction encoding scheme compatible with generic binaries

Compiler optimizations for code density of variable length instructions

Contact Info

Product

Resources

About