Performance Evaluation for System-on-Chip Architectures using Trace-based Transaction Level Simulation

Wild, Thomas; Herkersdorf, Andreas; Ohlendorf, Rainer

doi:10.1109/date.2006.244111

Cited by 14 publications

(7 citation statements)

References 12 publications

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“…They use a communication analysis graph that was obtained from a functional simulation, and gradually traced the vertices on the configured communication architecture to estimate computation and communication latency. Wild et al developed a transactionlevel modular approach for analyzing performance using SystemC as modeling language [15]. A developed architectural model simulates traces which record intercomponent transactions to increase the speed of performance estimation.…”

Section: Related Workmentioning

confidence: 99%

A fast and effective dynamic trace-based method for analyzing architectural performance

Chen¹,

Chiou²,

Chang³

2011

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)

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Performance estimation at system-level involves quantitative analysis to allow designers to evaluate alternative architectures before implementation. However, designers must spend a tremendous amount of time in system remodeling for performance estimation for each alternative solution in a huge design space. The effort required for system remodeling prolongs the exploration step. Furthermore, the accuracy and speed of performance analysis affects the effectiveness of architectural exploration. This work presents an architectural performance analysis using a dynamic trace-based method (APDT) to reduce the effort required for system remodeling and the time required to estimate performance during architecture exploration, thereby improving the effectiveness of that exploration. Experimental results demonstrate that the APDT approach is faster than the bus functional-level simulation on CoWare with a minor average deviation.

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Section: Related Workmentioning

confidence: 99%

A fast and effective dynamic trace-based method for analyzing architectural performance

Chen¹,

Chiou²,

Chang³

2011

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)

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“…This approach targets communication refinements of mixed accesses of local and shared memories via a shared bus. A more recent work proposed by Wild et al [13] uses trace-based simulation, targeting network processor architectures that consist of computation and memory modules communicating via a shared SoC bus. The drawback of these two last approaches is that the communication takes place only via a shared bus.…”

Section: Related Workmentioning

confidence: 99%

A modular fast simulation framework for stream-oriented MPSoC

Huang

Bacivarov

et al. 2009

2009 IEEE International Symposium on Industrial Embedded Systems

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Abstract-The performance estimation of complex multi-processor systems-on-chip (MPSoC) in a reasonable amount of time and with a good accuracy becomes more and more challenging due to the increasing number of embedded components and the resulting complex interactions. In this paper, we present a modular tracebased simulation framework, targeting the performance analysis of stream-oriented applications on complex MPSoC architectures. Our framework can analyze systems with a large number of hardware components, while considering various aspects like resource sharing, multi-hop communication, and memory allocation. We demonstrate the potential of our framework by real-life case studies and obtain a speedup of several orders of magnitude and an average accuracy of 97% when compared with the execution on a commercial instruction-accurate simulator.

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“…Another approach is trace-driven simulation which can be used to evaluate the performance [19], power consumption [4] or the memory access behavior [9] of computer systems. A trace is some information of interest generated during the execution of a program on a simple and fast simulation model.…”

Section: Related Workmentioning

confidence: 99%

Multiprocessor performance estimation using hybrid simulation

Gao

Karuri

Kraemer

et al. 2008

Proceedings of the 45th Annual Design Automation Conference

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With the growing number of programmable processing elements in today's MultiProcessor System-on-Chip (MPSoC) designs, the synergy required for the development of the hardware architecture and the software running on them is also increasing. In MPSoC development environment, changes in the hardware architecture can bring in extensive re-partitioning or re-parallelization of the software architecture. Fast and accurate functional simulation and performance estimation techniques are needed to cope with this co-design problem at the early phases of MPSoC design space exploration. The current paper addresses this issue by introducing a framework which combines hybrid simulation, cache simulation and online trace-driven replay techniques to accurately predict performance of programmable elements in an MPSoC environment. The resulting simulation technique can easily cope with the continuous re-organizations of software architectures during an Instruction Set Simulator (ISS) based design process. Experimental results show that this framework can improve system simulation speed by 3-5× on average while achieving accuracy closely comparable to traditional ISSes.

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Performance Evaluation for System-on-Chip Architectures using Trace-based Transaction Level Simulation

Cited by 14 publications

References 12 publications

A fast and effective dynamic trace-based method for analyzing architectural performance

A fast and effective dynamic trace-based method for analyzing architectural performance

A modular fast simulation framework for stream-oriented MPSoC

Multiprocessor performance estimation using hybrid simulation

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