Performance evaluation of a flow control algorithm for Network-on-Chip

Abstract

Network-on-chip (NoC) has been proposed for SoC (System-on-Chip) as an alternative to on-chip bus-based interconnects to achieve better performance and lower energy consumption. Several approaches have been proposed to deal with NoCs design and can be classified into two main categories, design-time approaches and run-time approaches. Design-time approaches are generally tailored for an application domain or a specific application by providing a customized NoC. All parameters, such as routing and switching schemes, are defined at design time. Run-time approaches, however, provide techniques that allow a NoC to continuously adapt its structure and its behavior (i.e., at runtime). In this paper, performance evaluation of a flow control algorithm for congestion avoidance in NoCs is presented. This algorithm allows NoC elements to dynamically adjust their inflow by using a feedback control-based mechanism. Analytical and simulation results are reported to show the viability of this mechanism for congestion avoidance in NoCs.

Flow control and scheduling mechanism to improve network performance in wireless NoC

“…In addition to various wireless technologies, several studies such as hop‐to‐hop flow control, end‐to‐end flow control, prediction‐based flow control and adaptive routing were analysed to alleviate the congestion in NoCs. The authors in [11] proposed a hop‐by‐hop flow control mechanism based on a compartmental fluid‐flow method for avoiding congestion in WiNoC. In the hop‐by‐hop flow control mechanism, the local information of congestion is exchanged between the router and its neighbours while in the end‐to‐end mechanism, control signals are sent to source and destination nodes to notify network congestion status.…”

Approaches for engineering adaptive systems in ubiquitous and pervasive environments

“…We have developed a run-time mechanism for congestion avoidance to allow Network-on-chip (NoC) elements to dynamically adjust their inflow by using a feedback controlbased mechanism [8]. An NoC is an-chip interconnect infrastructure used in system-on-chip designs to integrate hardware resources or cores [52].…”

“…The approach we have introduced in [8] mainly uses principles from feedback theory models and systems dynamics techniques [33,50] to prevent the NoC from being overloaded at run-time and then avoid buffer overflows inside the switches. The communication between two cores is characterized as flows that are represented by sequences of hops.…”