Performance Evaluation of Dynamic Circuit Specialization on Xilinx FPGAs

Kulkarni, Amit; Heyse, Karel; Davidson, Tom; Stroobandt, Dirk

doi:10.1145/2674095.2674096

Cited by 8 publications

(10 citation statements)

References 9 publications

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“…The application is processed to yield a Template Configuration (TC) and a Partial Parameterized Configuration (PPC). A detailed explanation on each step of the generic stage is explained in [5].…”

Section: B Tool Flow For Parameterized Configurationmentioning

confidence: 99%

“…However, in the parameterized VCGRA implementation, the settings registers of each PE and the routing switches are updated by reconfiguring each frame of the FPGA that contains setting bits of the VCGRA. This is usually accomplished by read-modify and write back frames of the FPGA (microreconfiguration [5]). …”

Section: Limitation Of Parameterized Vcgrasmentioning

confidence: 99%

“…However, this gain does not come for free. There exist a reconfiguration overhead such as reconfiguration time, Boolean function evaluation time and the PPC memory [5]. The estimated reconfiguration time depending on the number of TLUTs and TCONs for one PE is 251 ms.…”

Section: A Fully Parameterized 4x4 Vcgra Gridmentioning

confidence: 99%

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A Fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications

Kulkarni

Vasteenkiste

Stroobandt

et al. 2016

2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

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Abstract-Field Programmable Gate Arrays (FPGAs) have proven their potential in accelerating High Performance Computing (HPC) Applications. Conventionally such accelerators predominantly use, FPGAs that contain fine-grained elements such as LookUp Tables (LUTs), Switch Blocks (SB) and Connection Blocks (CB) as basic programmable logic blocks. However, the conventional implementation suffers from high reconfiguration and development costs. In order to solve this problem, programmable logic components are defined at a virtual higher abstraction level. These components are called Processing Elements (PEs) and the group of PEs along with the inter-connection network form an architecture called a Virtual Coarse-Grained Reconfigurable Array (VCGRA). The abstraction helps to reconfigure the PEs faster at the intermediate level than at the lower-level of an FPGA.Conventional VCGRA implementations (built on top of the lower levels of the FPGA) use functional resources such as LUTs to establish required connections (intra-connect) within a PE. In this paper, we propose to use the parameterized reconfiguration technique to implement the intra-connections of each PE with the aim to reduce the FPGA resource utilization (LUTs). The technique is used to parameterize the intra-connections with parameters that only change their value infrequently (whenever a new VCGRA function has to be reconfigured) and that are implemented as constants. Since the design is optimized for these constants at every moment in time, this reduces the resource utilization. Further, interconnections (network between the multiple PEs) of the VCGRA grid can also be parameterized so that both the inter-and intraconnect network of the VCGRA grid can be mapped onto the physical switch blocks of the FPGA. For every change in parameter values a specialized bitstream is generated on the fly and the FPGA is reconfigured using the parameterized run-time reconfiguration technique. Our results show a drastic reduction in FPGA LUT resource utilization in the PE by at least 30% and in the intra-network of the PE by 31% when implementing an HPC application.

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Section: B Tool Flow For Parameterized Configurationmentioning

confidence: 99%

Section: Limitation Of Parameterized Vcgrasmentioning

confidence: 99%

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A Fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications

Kulkarni

Vasteenkiste

Stroobandt

et al. 2016

2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

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“…The reconfiguration is performed using a HWICAP driver "XHwIcap_SetClbBits" function [6]. The two crucial arguments of this function are: 1) Location co-ordinates of a TLUT: using this information, the frame address is generated that is used to point to the frame which contains the truth table entries of the TLUT.…”

Section: State Of the Artmentioning

confidence: 99%

Power measurements and analysis for dynamic circuit specialization

Kulkarni

Bonamy²,

Stroobandt

2015

2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

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Abstract-Dynamic Circuit Specialization (DCS) is a technique for optimized FPGA implementation and is built on top of Partial Reconfiguration (PR). Dynamic Partial Reconfiguration (DPR) provides an opportunity to share the silicon area between different Partially Reconfigurable Modules (PRMs) and therefore results in smaller and faster designs that potentially also reduce the power consumption. In this paper, we show that energy consumption is an important factor that has to be considered while implementing a parameterized design using DCS. In order to make a good choice for implementing a parameterized design with the goal of power optimized implementation, it is important to have a good power consumption estimate of the Dynamic Circuit Specialization. In this context, our paper presents a detailed investigation of the power consumption of a parameterized design implemented using DCS on the Xilinx Zynq-SoC FPGA. We propose an energy analysis of DCS and investigate the benefits of the use of DCS in comparison with a classic static FPGA implementation. We see that the power needed for the reconfiguration is much higher than the gain in power using the reconfiguration over the static implementation. An important reason is because of the CPU involved during the reconfiguration and the interface between the AXI bus and the HWICAP. To reduce the reconfiguration power, we include a clock gating technique to the reconfiguration interface AXI-HWICAP that makes DCS more power efficient. We also relate the power gain to the size of the implementation and to the allowed time to reconfigure versus the useful run time. We conclude that for an implementation with 10 FIR filters, the reconfiguration time should not take more than 30.3% of the total time in order to remain energy efficient. Considering a specific use case with 10 FIR filters at a reconfiguration rate of 0.01, the energy consumption using DCS implementation is 20.5% lower than using the static FIR.

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“…The message processor, π-function, and ARX engine for 16-bit version of π-Cipher are implemented and evaluated in an FPGA using a Xilinx Virtex-7. In order to optimize the implementation of the processor on the FPGA, we make use of parameterized configuration technique [14] that optimizes the key generation module and contributes in the reduction of the resource utilization of the processor.…”

Section: Introductionmentioning

confidence: 99%

A 16-Bit Reconfigurable Encryption Processor for p-Cipher

El-Hadedy

Mihajloska

Gligoroski

et al. 2016

2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

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Abstract-This paper presents an improved hardware implementation of a 16-bit ARX (Add, Rotate, and Xor) engine for one of the CAESAR second-round competition candidates, π-Cipher, implemented on an FPGA. π-Cipher is a nonce-based authenticated encryption cipher with associated data. The security of the π-Cipher relies on an ARX based permutation function, which is denoted as a π-function. The proposed ARX engine has been implemented in just 266 slices, which includes the buffers of the input and the output. It can be clocked at 347 MHz. Also, in this paper, a message processor based on the proposed ARX engine is introduced. The message processor has been implemented in 1114 slices and it can be clocked at 250 MHz. The functionality of the proposed ARX engine was verified on the Xilinx Virtex-7. The new design of the ARX engine allows for almost four times speedup in performance while consuming only 17% larger area than previously published work. We extend our message processor implementation by using parametrized reconfiguration technique after which an area reduction of 27 slices is observed.

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Performance Evaluation of Dynamic Circuit Specialization on Xilinx FPGAs

Cited by 8 publications

References 9 publications

A Fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications

A Fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications

Power measurements and analysis for dynamic circuit specialization

A 16-Bit Reconfigurable Encryption Processor for p-Cipher

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