Performance Evaluation of Efficient XOR Structures in Quantum-Dot Cellular Automata (QCA)

Abstract

<p class="MsoNormal" style="text-align:justify;"> <span lang="EN-US">Quantum-dot cellular automaton (QCA) is an emerging, promising, future generation nanoelectronic computational architecture that encodes binary information as electronic charge configuration of a cell. It is a digital logic architecture that uses single electrons in arrays of quantum dots to perform binary operations. Fundamental unit in building of QCA circuits is a QCA cell. A QCA cell is an elementary building block which can be used to build basic gates and logic devices in QCA architectures. This paper evaluates the performance of various implementations of QCA based XOR gates and proposes various novel layouts with better performance parameters. We presented the various QCA circuit design methodology for XOR gate. These layouts show less number of crossovers and lesser cell count as compared to the conventional layouts already present in the literature. These design topologies have special functions in communica</span><span lang="EN-US">tion based circuit applications. They are particularly useful in phase detectors in digital circuits, arithmetic operations and error detection & correction circuits. The comparison of various circuit designs is also given. The proposed designs can be effectively used to realize more complex circuits. The simulations in the present work have been carried out us</span><span lang="EN-US">ing QCADesigner tool.</span><span lang="EN-US"><o:p></o:p></span> </p

Design of Area-Delay Efficient Adder Based Circuits in Quantum Dot Cellular Automata

“…The physical implementation of an automaton using quantum-dot cells automaton quickly gained popularity by replacing the CMOS technology [4][5].Method [6] describes the different XOR gate structures in quantum dot cellular automata. Method [7] describes a full adder layout with 150 cells and 9 Majority Gate with 2.25 delay and area of 0.28 µm 2 .…”

Two Dimensional QCA XOR Logic Using NNI Gate

“…It uses 52 cells but there is unnecessary space. Beigh"s XOR requires a crossover wire with more clocks and cells due to connection of input B. Beigh"s design [27] has more clocks than other XOR gate in Table 3. The proposed XOR has 4 clocks and smaller cell count and circuit area.…”

“…Walus"s XOR uses 83 cells and 4 clocks. Beigh"s QCA XOR gate and simulation shows in Figure 9 [27]. Input A and B are at the corner of wire and propagate signal to different direction.…”

Novel Optimized Designs for QCA Serial Adders

“…In this design, XOR Gate and JK flip-flop are used instead of the full adder and D flip-flop in the previous design, respectively [24]. The circuit diagrams and QCA layouts of XOR Gate and JK flip-flop are shown in Fig.14 and Fig.15, respectively [22,25]. Fig.16 shows the circuit diagram and QCA layout of the third proposed QCA serial adder.…”