Performance Evaluation of NAS Parallel Benchmarks on Intel Xeon Phi

Ramachandran, Arunmoezhi; Vienne, J.; Wijngaart, Rob Van der; Koesterke, L.; Sharapov, Ilya

doi:10.1109/icpp.2013.87

Cited by 36 publications

(28 citation statements)

References 8 publications

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“…Paper [6] describes some opportunities and challenges about porting to the Intel Xeon Phi. Paper [7] makes a brief performance comparison of NAS Parallel Benchmarks running on CPU and MIC separately. But this research does not combine the computation power of MIC with CPU to display higher efficiency of CPU/MIC heterogeneous node.…”

Section: Related Workmentioning

confidence: 99%

A Method to Analyze and Optimize Parallel Programs on CPU/MIC Heterogeneous Architecture

Li¹,

Wang²

2017

dtcse

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Abstract. Cooperating with the Intel® Many Integrated Core Architecture which was announced in 2010 as a massively parallel coprocessor, heterogeneous node has been broadly applied in petascale supercomputers, such as TianHe-II. The performance analysis for massive parallel applications under the heterogeneous architecture is playing an important role for next generation exascale supercomputers. In this paper, we proposed a method to analyze and optimize parallel programs running on CPU/MIC heterogeneous computing node with offload programming mode. To monitor runtime behaviors in offload process, we used TAU to instrument the offload code region to collect performance events. Then we compared the performance of different programming modes with NAS Parallel Benchmarks. The results indicated that asynchronous offload mode performs better than synchronous offload mode.

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Section: Related Workmentioning

confidence: 99%

A Method to Analyze and Optimize Parallel Programs on CPU/MIC Heterogeneous Architecture

Li¹,

Wang²

2017

dtcse

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“…Scientific and engineering applications have small instruction footprints, long basic blocks, and low control divergence which makes them suitable for SIMD execution. Nowadays, Intel's Xeon Phi cores [27] and Fujitsu's SPARC64 series of chips [28] implement wide vector units to exploit these code characteristics and gain performance. Our work revisits these findings considering modern HPC workloads and in the context of CMPs made out of light-weight out-of-order cores.…”

Section: Related Workmentioning

confidence: 99%

“…Because of that, ARM's Cortex-A57 cores, used in microservers, have a larger 48 KB I-cache to reduce the impact of I-cache misses [34]. An Intel Xeon Phi core has 512-bit wide vector processing unit so it can exploit the SIMD characteristics of scientific codes [27]. Our findings suggest that a similar core tailoring can be applied to lean-core CMPs used in HPC by redimensioning the existing structures based on application demands.…”

Section: Related Workmentioning

confidence: 99%

Rebalancing the core front-end through HPC code analysis

Milić

Carpenter

Rico

et al. 2016

2016 IEEE International Symposium on Workload Characterization (IISWC)

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Abstract-There is a need to increase performance under the same power and area envelope to achieve Exascale technology in high performance computing (HPC). The today's chip multiprocessor (CMP) design is tailored by traditional desktop and server workloads, different from parallel applications commonly run in HPC. In this work, we focus on the HPC code characteristics and processor front-end which factors around 30% of core power and area on the emerging lean-core type of processors used in HPC. Separating serial from parallel code sections inside applications, we characterize three HPC benchmark suites and compare them to a traditional set of desktop integer workloads. HPC applications have biased and mostly backward taken branches, small dynamic instruction footprints, and long basic blocks. Our findings suggest smaller branch predictors (BP) with the additional loop BP, smaller branch target buffers (BTB), and smaller L1 instruction caches (I-cache) with wider lines. Still, the aforementioned downsizing applies only to the cores meant to run parallel code. The difference between serial and parallel code sections in HPC applications points to an asymmetric CMP design, with one baseline core for sequential and many HPCtailored cores designed for parallel code. Predictions using Sniper simulator and McPAT show that an HPC-tailored lean core saves 16% of the core area and 7% of power compared to a baseline core, without performance loss. Using the area savings to add an extra core, an asymmetric CMP with one baseline and eight tailored cores has the same area budget as a symmetric CMP composed out of eight baseline cores demanding 4% more power and providing 12% shorter execution time on average.

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“…NAS application benchmarks of class B (medium) and C (large) are executed on Linux kernel version 2.6.32. These benchmarks feature wide variations in several execution properties, including parallelization annotations, varying sequential parts and compute-and memory-boundedness of threads [14]. The applications were initially profiled and performance annotated with execution times (Section III-A).…”

Section: A Experimental Setupmentioning

confidence: 99%

Adaptive Energy Minimization of OpenMP Parallel Applications on Many-Core Systems

Shafik

Das

Yang

et al. 2015

Proceedings of the 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures

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Abstract-Energy minimization of parallel applications is an emerging challenge for current and future generations of manycore computing systems. In this paper, we propose a novel and scalable energy minimization approach that suitably applies DVFS in the sequential part and jointly considers DVFS and dynamic core allocations in the parallel part. Fundamental to this approach is an iterative learning based control algorithm that adapt the voltage/frequency scaling and core allocations dynamically based on workload predictions and is guided by the CPU performance counters at regular intervals. The adaptation is facilitated through performance annotations in the application codes, defined in a modified OpenMP runtime library. The proposed approach is validated on an Intel Xeon E5-2630 platform with up to 24 CPUs running NAS parallel benchmark applications. We show that our proposed approach can effectively adapt to different architecture and core allocations and minimize energy consumption by up to 17% compared to the existing approaches for a given performance requirement.Keywords-Many-core, OpenMP, Energy minimization.I. INTRODUCTION Silicon technology scaling has enabled the fabrication of many interconnected cores on a single chip for current and future generations of computing systems. The emergence of such systems has facilitated computing performance at unprecedented levels with application parallelization and architectural support. However, higher device-level integration and operating frequency in these systems have rendered exponentially increased power density and energy consumption [1]. Hence, minimizing the energy consumption, while delivering the required performance is a key design challenge for many-core applications [2], [5].The continuing performance growth of many-core applications has been facilitated by parallel programming models. OpenMP is one such programming model, considered as the de facto standard of shared memory multiprocessing [3]. It features compiler-enabled annotations that can achieve data-or task-level parallelization. The parallelization is facilitated by runtime libraries that can allocate the number of computing nodes and suitably schedule the parallel tasks and threads during runtime to achieve high performance [9].Over the years, there has been growing interest in OpenMP-based dynamic adaptation between energy and performance trade-offs of parallel applications [4]. Dynamic voltage/frequency scaling (DVFS) is a major runtime control knob to achieve such adaptation. The main principle of DVFS is to suitably lower the operating voltage/frequency to exponentially reduce the energy consumption at the cost of linear performance degradation [5]. Shirako et al.[10] proposed a DVFS-based energy minimization approach using a modified OpenMP compiler, named OSCAR. The compiler analyses the criticality of various parallel tasks and sections and identifies suitable DVFS for them. Cochran et al. [11] proposed another adaptive DVFS approach to control the peak power budget of an applicati...

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Performance Evaluation of NAS Parallel Benchmarks on Intel Xeon Phi

Cited by 36 publications

References 8 publications

A Method to Analyze and Optimize Parallel Programs on CPU/MIC Heterogeneous Architecture

A Method to Analyze and Optimize Parallel Programs on CPU/MIC Heterogeneous Architecture

Rebalancing the core front-end through HPC code analysis

Adaptive Energy Minimization of OpenMP Parallel Applications on Many-Core Systems

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