Performance Evaluation of PDES on Multi-core Clusters

Abstract

Abstract-Trends in VLSI and microarchitecture design have ushered in the multi-core era, where the number of cores on a chip is expected to grow with every processor generation. Soon, each chip will have a large number of tightly integrated processing cores with communication latencies substantially lower than those present in conventional clusters. Clusters made of such microprocessors experience non-uniform latencies between cores: cores on the same chip can communicate faster than cores on different chips; cores on the same machine can communicate faster than cores on different machines. In this paper, we characterize the performance of PDES models on a cluster of dual quad-core machines using a parameterizable modified version of Phold, a standard benchmark for parallel simulation.We study various combinations of regional and remote communication patterns to quantify the impact of communication on overall performance of simulation. We discover that the amount of communication has determining impact and it's essential to optimize this communication at each level to take maximum advantage of multi-core platform. We show that partitioning significantly improves performance. We also explore the impact of load imbalance on application performance and provide critical insight into how to partition for these different environments. We believe that this study represents a significant first step in characterizing the performance space for PDES on this emerging platform.

Can PDES scale in environments with heterogeneous delays?

“…Scalability studies of PDES on a blue gene supercomputer demonstrate that scalability up to thousands of processors can be achieved due to the low communication latency [22,3]. In [21], a multi-process based PDES kernel is used to evaluate the performance on both multi-core clusters and traditional clusters, and shows that a better performance can be achieved on CMs. Wilsey et al [12] proposed an algorithm to allow dynamic core frequency adjustment during Time Warp simulations on multicores.…”

Exploring many-core architecture design space for parallel discrete event simulation

“…The continuing emergence of multi-core and many-core architectures offers a significant promise with respect to PDES performance. Several recent studies evaluated the performance impact of multi-core chips on PDES [2,14,15,7,31]. However, these studies are limited to the existing hardware platforms with modest number of cores per chip [2,14], or to specialized chips with larger core counts, such as the Tilera Tile64 architecture [15].…”

“…Several recent studies evaluated the performance impact of multi-core chips on PDES [2,14,15,7,31]. However, these studies are limited to the existing hardware platforms with modest number of cores per chip [2,14], or to specialized chips with larger core counts, such as the Tilera Tile64 architecture [15]. Therefore, while these prior works are still useful and more such studies are likely to emerge as the new multi-core processors are developed and brought to market, they can only answer a limited set of questions, and it is unclear whether the conclusions of these studies can be easily generalized beyond specific platforms and organizations being investigated.…”

Characterizing and Understanding PDES Behavior on Tilera Architecture

“…Recently, continuing emergence of multicore processors and the potential of these architectures to drastically minimize the impact of communication-related issues motivated several studies that examine performance and scalability of PDES in these environments [1], [2]. For example, the work of [2] demonstrated the advantages of using multithreaded (as opposed to multiprocess) implementation of ROSS simulator [3] on a quad-core Intel Core i7 machine and on a AMD Magny-cours system [4] composed of four 12-core chips for the total of 48 cores.…”