Performance Evaluation of Pipelined Communication Combined with Computation in OpenCL Programming on FPGA

Fujita, Norihisa; Kobayashi, Ryohei; Yamaguchi, Yoshiki; Ueno, Tomohiro; Sano, Kentaro; Boku, Taisuke

doi:10.1109/ipdpsw50202.2020.00083

Cited by 20 publications

(7 citation statements)

References 9 publications

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“…However, their programming complexity can be a problem. So multiple higher-level solutions have been developed [16]. OpenCL is an open programming standard for heterogeneous computing that provides a unified C programming model.…”

Section: Related Work a New Applications In The Smart Gridmentioning

confidence: 99%

“…OpenCL is an open programming standard for heterogeneous computing that provides a unified C programming model. Fujita et al [16] proposed a so called Communication Integrated Reconfigurable CompUting System (CIRCUS) to facilitate the high-speed interconnection of FPGAs from OpenCL. They explained that it is possible to accelerate HPC applications on FPGA by combining computation and communication.…”

Section: Related Work a New Applications In The Smart Gridmentioning

confidence: 99%

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High-Performance Computing Architecture for Sample Value Processing in the Smart Grid

et al. 2022

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Section: Related Work a New Applications In The Smart Gridmentioning

confidence: 99%

Section: Related Work a New Applications In The Smart Gridmentioning

confidence: 99%

High-Performance Computing Architecture for Sample Value Processing in the Smart Grid

et al. 2022

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“…Some FPGA supercomputers use a PCIe network for interconnection between FPGAs and GPUs [21], [22]. High-speed serial links of more than 40 Gbps are also used [2]- [4] between FPGA boards. Although a large bandwidth is provided, they required expensive optical cables, interface chips, and high-level board-implementation techniques.…”

Section: Interconnection Network Of Multi-fpga Systemsmentioning

confidence: 99%

“…Some multi-FPGA systems use extremely high-speed links of more than 40 Gbps [2]- [4], while FiC uses costefficient GTH serial links each of which supports 9.9-Gbps transfer speed. It provides 32 bi-directional lanes per board to maintain the total bandwidth.…”

Section: Introductionmentioning

confidence: 99%

Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System

Ito

Iizuka

Hironaka

et al. 2021

IEICE Trans. Inf. & Syst.

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“…In particular, the Xilinx Vitis and Intel FPGA SDK for OpenCL are an all-inone development environment that hide from the user the fundamental parts of FPGA implementation, such as external memory controllers, the PCIe interface, and device drivers, enabling implementation of FPGA applications without the user being aware of them. The Intel FPGA SDK for OpenCL provides a mechanism for controlling the peripherals for the FPGA fabric from OpenCL, and we previously proposed a framework [1] using the mechanism to assist application developers in developing HPC applications in the OpenCL programming layer. Therefore, we believe that the Intel FPGA SDK for OpenCL is currently the best solution for application developers when using FPGAs.…”

Section: Introductionmentioning

confidence: 99%

An Open-source FPGA Library for Data Sorting

Kobayashi

Miura

Fujita

et al. 2022

Journal of Information Processing

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Field-programmable gate arrays (FPGAs) have garnered significant interest in research on highperformance computing because their flexibility enables the building of application-specific computation pipelines and data supply systems. In addition to the flexibility, toolchains for the development of FPGAs in OpenCL have been developed and offered by FPGA vendors that reduce the programming effort required. However, the high level of abstraction in the OpenCL-based development approach is a disadvantage, making it difficult to perform fine-grained performance tuning. In this paper, we present one of the methodologies to achieve both the reduction of FPGA programming cost and the provision of high performance. We focus on data sorting, which is a basic arithmetic operation, and we introduce a sorting library that can be used with the OpenCL programming model for FPGAs. Our sorting library has so far only supported integer data, but in this paper, we propose a new method that supports floating-point data. It consumes at least twice as many hardware resources compared to the merge sort restructured for the OpenCL programming model for FPGAs. However, its operating frequency is 1.08x higher and its sorting throughput is three orders of magnitude greater than the baseline. The source code of our sorting library is open source, and it can be used by application developers around the world.

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Performance Evaluation of Pipelined Communication Combined with Computation in OpenCL Programming on FPGA

Cited by 20 publications

References 9 publications

High-Performance Computing Architecture for Sample Value Processing in the Smart Grid

High-Performance Computing Architecture for Sample Value Processing in the Smart Grid

Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System

An Open-source FPGA Library for Data Sorting

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