Performance evaluation of the low-voltage CML D-latch topology

Design Techniques for Low-Power Cascaded CML Gates

“…The model in (1) has also been shown to be valid for low-voltage triple-tail cells, other than the traditional series gates [12]- [13]. By considering that the power consumption is almost static and determined by the bias current I SS , the power consumption of a CML gate is equal to V DD ⋅I SS .…”

“…The resulting delay after optimally sizing the bias currents according to (13) is obtained by substituting it into (8), thereby leading to…”

“…(14) expresses the delay of an optimized path having an assigned value of the overall bias current I TOT derived from considerations on the power budget at the system level, or allows for easily evaluating the overall bias current I TOT to achieve a given path delay constraint τ PD . In both cases, I TOT has a well-known value, and gates' bias currents can be optimally sized by resorting to (13).…”

“…An HSB2 bipolar process (by courtesy of STMicroelectronics) was adopted. The resulting values of the coefficients a i and b i , evaluated according to the methodology in [10]- [11], [13], are reported in Table I, where it has been considered that LATCH1, LATCH2 and MUX in Fig. 2 have a fan-out of 7, 1, and 1, respectively, and the load capacitance C L of the BUFFER gate is assumed to be equal to 100 fF (i.e.…”

“…By assuming a typical power budget of 0.6 mW, the overall bias current I TOT results to 500 µA, which is much lower than I TOTop , thus criteria in Section IIIB can be applied. From Table II, coefficient B in (14b) results to 1.59E-12, thus the overall path delay (14a) results to 3.18 ns, whereas the resulting bias current of the four gates, evaluated by using (13), are reported in Table II. This table, which also reports the simulated gate delay values and the model error compared to simulations, confirms the good agreement of theoretical results with simulations.…”