Performance Implications of Extended Page Tables on Virtualized x86 Processors

Merrifield, Timothy; Taheri, Hassan

doi:10.1145/2892242.2892258

Cited by 26 publications

(6 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This is contrary to some published experiments, for example, VMware have conducted a performance evaluation of EPT in VMware [2009], which shows that EPT can improve performance of MMU-intensive benchmarks by 48% and MMU microbenchmarks by up to 600%. However, our measurement of the impact of EPT on the SPEC CPU2006 benchmarks shows that the performance increase is negligible, which is also the conclusion drawn by Buell et al [2013] and Merrifield and Taheri [2016]. Figure 13 shows the relative performance Fig. 14.…”

Section: Additional Hardware Support For Mmu Virtualizationsupporting

confidence: 82%

Hardware-Accelerated Cross-Architecture Full-System Virtualization

Spink

Wagstaff

Franke

2016

ACM Trans. Archit. Code Optim.

View full text Add to dashboard Cite

Hardware virtualization solutions provide users with benefits ranging from application isolation through server consolidation to improved disaster recovery and faster server provisioning. While hardware assistance for virtualization is supported by all major processor architectures, including Intel, ARM, PowerPC, and MIPS, these extensions are targeted at virtualization of the same architecture, for example, an x86 guest on an x86 host system. Existing techniques for cross-architecture virtualization, for example, an ARM guest on an x86 host, still incur a substantial overhead for CPU, memory, and I/O virtualization due to the necessity for software emulation of these mismatched system components. In this article, we present a new hardwareaccelerated hypervisor called CAPTIVE, employing a range of novel techniques that exploit existing hardware virtualization extensions for improving the performance of full-system cross-platform virtualization. We illustrate how (1) guest memory management unit (MMU) events and operations can be mapped onto host memory virtualization extensions, eliminating the need for costly software MMU emulation, (2) a block-based dynamic binary translation engine inside the virtual machine can improve CPU virtualization performance, (3) memory-mapped guest I/O can be efficiently translated to fast I/O specific calls to emulated devices, and (4) the cost for asynchronous guest interrupts can be reduced. For an ARM-based Linux guest system running on an x86 host with Intel VT support, we demonstrate application performance levels, based on SPEC CPU2006 benchmarks, of up to 5.88× over state-of-the-art QEMU and 2.5× on average, achieving a guest dynamic instruction throughput of up to 1280 MIPS (million instructions per second) and 915.52 MIPS, on average.

show abstract

Section: Additional Hardware Support For Mmu Virtualizationsupporting

confidence: 82%

Hardware-Accelerated Cross-Architecture Full-System Virtualization

Spink

Wagstaff

Franke

2016

ACM Trans. Archit. Code Optim.

View full text Add to dashboard Cite

show abstract

“…The vMMU uses a Virtual Processor IDentifier (VPID) to identify the TLB cache lines utilized by both VMs and VMM. More specifically, the VPID avoids the TLB cache flush during VM-VMM transitions with an Extended Page-Table (EPT) [97] mechanism that employs hardware based nested address translation (see Sec. III-B2b).…”

Section: ) Hypervisorsmentioning

confidence: 99%

Operating Systems and Hypervisors for Network Functions: A Survey of Enabling Technologies and Research Studies

et al. 2022

View full text Add to dashboard Cite

Scalable and flexible communication networks increasingly conduct the packet processing for Network Functions (NFs) in General Purpose Computing (GPC) platforms. The input/output (I/O)-intensive and latency-sensitive packet processing is challenging for the operating systems and hypervisors running on GPC platforms. This article surveys the existing enabling technologies and research studies on operating system and hypervisor aspects that directly influence the packet processing for NFs on GPC platforms. We organize this survey according to the main categories abstraction approach, memory access, and I/O strategy. We further categorize abstraction approach technologies and research studies into the categories operation systems, hypervisors, and containers. We partition the memory access category into the two subcategories of memory allocation and memory access, while we partition the I/O strategy category into the sub-categories I/O device virtualization and I/O device access. Our survey gives a comprehensive summary of the capabilities and limitations of the existing enabling technologies and researched approaches for abstraction, memory access, and I/O for NF packet processing. We outline critical future research directions for advancing NF packet processing on GPC platforms.

show abstract

“…More profound work tends to have a very narrow scope, e.g. nested paging [61], NUMA locality [47] or I/O [62]. Nevertheless, these studies have pinpointed various major causes of virtualization overhead, such as false cache sharing, extra iTLB misses and poor I/O performance, resulting in various hardware improvements being implemented [11], [63].…”

Section: Related Workmentioning

confidence: 99%

Virtualization Overhead of Multithreading in X86 State-of-the-Art & Remaining Challenges

Schildermans

Shan

Aerts

et al. 2021

IEEE Trans. Parallel Distrib. Syst.

View full text Add to dashboard Cite

Despite great advancements in hardware-assisted virtualization of the x86 architecture, certain workloads still suffer significant overhead. This work dissects said overhead in the context of multi-threading. We describe the state of the art, pinpoint challenges and suggest improvements, aiming to provide a valuable reference to developers and users of virtualization systems alike. We study the virtualization overhead of the PARSEC and SPLASH2X multithreaded benchmarks in a variety of scenarios using a state-of-the-art system. Through controlled experiments, source code analysis and literature review, we quantify the virtualization overhead multithreading still induces and link it to its root causes, after which we suggest possible mitigation strategies. Multithreading still induces high virtualization overhead, mainly caused by synchronization, spinning at user level and NUMA management. The overhead is diverse in nature and embodiment as it is a function of many system and workload properties. System-level solutions are feasible, but often imply difficult trade-offs. Systematic workload optimization is a promising alternative.

show abstract

Performance Implications of Extended Page Tables on Virtualized x86 Processors

Cited by 26 publications

References 13 publications

Hardware-Accelerated Cross-Architecture Full-System Virtualization

Hardware-Accelerated Cross-Architecture Full-System Virtualization

Operating Systems and Hypervisors for Network Functions: A Survey of Enabling Technologies and Research Studies

Virtualization Overhead of Multithreading in X86 State-of-the-Art & Remaining Challenges

Contact Info

Product

Resources

About