Performance improvement of nc-Si nonvolatile memory by novel design of tunnel and control layer

Qian, Xinye; Chen, Kunji; Ma, Zhongyuan; Zhang, Xiangao; Fang, Zhong-Hui; Liu, Guangyuan; Jiang, Xiaofan; Huang, Xinfan

doi:10.1109/icsict.2010.5667491

Cited by 1 publication

(2 citation statements)

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“…As the charges stored in the floating-gate layer can be free to move laterally, it results in data loss. To solve the current leakage problems, the nanocrystal has been adapted to the floating-gate memory [ 8 , 9 , 10 , 11 ]. In contrast to the polysilicon floating gate, using discrete nanocrystals as the charge storage layer can avoid the free movement of charges laterally in the floating-gate layer, thus effectively preventing data loss caused by charge leakage [ 12 , 13 , 14 ].…”

Section: Introductionmentioning

confidence: 99%

“…In contrast to the polysilicon floating gate, using discrete nanocrystals as the charge storage layer can avoid the free movement of charges laterally in the floating-gate layer, thus effectively preventing data loss caused by charge leakage [ 12 , 13 , 14 ]. In addition, the ultra-thin tunnel oxide layer in the nanocrystal floating-gate memory has the advantages of low power consumption and high erasing/programming speed [ 9 , 10 , 11 ]. The research on nanocrystal floating-gate memory is extensive, from traditional silicon germanium materials to third-generation semiconductor materials of SiC [ 15 , 16 , 17 ].…”

Section: Introductionmentioning

confidence: 99%

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Controlling the Carrier Injection Efficiency in 3D Nanocrystalline Silicon Floating Gate Memory by Novel Design of Control Layer

et al. 2023

Nanomaterials

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Three-dimensional NAND flash memory with high carrier injection efficiency has been of great interest to computing in memory for its stronger capability to deal with big data than that of conventional von Neumann architecture. Here, we first report the carrier injection efficiency of 3D NAND flash memory based on a nanocrystalline silicon floating gate, which can be controlled by a novel design of the control layer. The carrier injection efficiency in nanocrystalline Si can be monitored by the capacitance–voltage (C–V) hysteresis direction of an nc-Si floating-gate MOS structure. When the control layer thickness of the nanocrystalline silicon floating gate is 25 nm, the C–V hysteresis always maintains the counterclockwise direction under different step sizes of scanning bias. In contrast, the direction of the C–V hysteresis can be changed from counterclockwise to clockwise when the thickness of the control barrier is reduced to 22 nm. The clockwise direction of the C–V curve is due to the carrier injection from the top electrode into the defect state of the SiNx control layer. Our discovery illustrates that the thicker SiNx control layer can block the transfer of carriers from the top electrode to the SiNx, thereby improving the carrier injection efficiency from the Si substrate to the nc-Si layer. The relationship between the carrier injection and the C–V hysteresis direction is further revealed by using the energy band model, thus explaining the transition mechanism of the C–V hysteresis direction. Our report is conducive to optimizing the performance of 3D NAND flash memory based on an nc-Si floating gate, which will be better used in the field of in-memory computing.

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