Performance improvement of PFSCL gates through capacitive coupling

Abstract

In this paper, a new positive feedback sourcecoupled logic (PFSCL) style with higher speed than the existing PFSCL style is proposed. The proposed logic style replaces the load in existing PFSCL with a new load which exhibits capacitive coupling that enhances the switching speed of the circuits. The mechanism of capacitive coupling is modeled and its effect on the propagation delay is described. SPICE simulations to validate the proposed theory have been carried out with TSMC 0.18 µm CMOS technology parameters. Several PFSCL logic gates such as inverter, NAND2, NOR2, NOR3 based on the proposed logic style are implemented and their performance is compared with the existing PFSCL logic gates. It is found that the logic gates based on the proposed PFSCL style lowers the propagation delay by 31 percent.