Performance investigation of different low power SRAM cell topologies using stacked-channel tri-gate junctionless FinFET

Singh, Devenderpal; Chaudhary, Shalini; Dewan, Basudha; Yadav, Menka

doi:10.1016/j.mejo.2024.106122

Cited by 1 publication

(2 citation statements)

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“…At a supply voltage equal to 1 volt, the RSNM, HSNM, and WNM of the SRAM cell with FinFET logic are reported to be 285 mV, 360 mV, and 302 mV, respectively. As per existing literatures [44,45], value of RSNM, HSNM and WNM is reported in between 105 to 115 mV, 280 to 300 mV, 1.94 mV to 230 mV respectively. In comparison to the traditional 6 T FinFET SRAM cell, the suggested FinFET SRAM cell likewise exhibits greater HSNM.…”

Section: Finfet Application As Inverter and Sramsupporting

confidence: 75%

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Simulation based analysis of HK-Ge-Step-FinFET and its usage as inverter & SRAM

Gopal,

Goswami,

Johar

et al. 2024

Phys. Scr.

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This paper deals with comparative simulation of High-k dielectrics -Germanium Step FinFET (HK-Ge-Step-FinFET) device with reference Step FinFET. For the first time we have investigated the impact of various dimensional parameters like oxide thickness tox, gate length Lg, drain bias voltage Vds on the performance of Proposed and Reference FinFET devices. These FinFET structures have been designed and simulated in Sentaurus TCAD and Cadence Virtuoso. The electrical parameters such as current ratio ION/IOFF , Sub-threshold Swing SS , Drain Induced Barrier Lowering (DIBL), threshold voltage Vth, gate capacitance, intrinsic delay and transconductance are extracted at 10 nm gate length. It is noticed that there is a significant improvement of 28 times and 23 times in ION for proposed device over reference FinFET at Vds = 1 V and Vds = 0.5 V respectively, improvement in ION/IOFF ratio from 8.05 ×108 to 6.65 ×1010, SS of 63.21 mV/decade to 61.5 mV/decade and excellent threshold voltage of 0.18 V in proposed FinFET. The characteristics of the proposed SRAM cell including, static noise margin (SNM), read/write delay, and subthreshold leakage power, are compared with the conventional 6T SRAM cells. It is reported that the FinFET SRAM cell has RSNM, HSNM, and WNM of 285 mV, 360 mV, and 302 mV, respectively, at Vds = 1 V. Furthermore, the suggested device-based SRAM cell outperforms traditional SRAM cells at 1.0 V in terms of read noise margin, hold noise margin, and write noise margin, as well as leakage power. Thus, it may prove to be a viable option for lowering leakage components, making it effective for low-power and high-performance inverter and SRAM cell design in the nanoscale regime.

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Section: Finfet Application As Inverter and Sramsupporting

confidence: 75%

“…Higher RSNM SRAM cells are more resistant to read failures. I READ is the current drawn during read operation from the bit-line attached to a storage node holding a '0' [43][44][45]. A smaller TR results from a faster discharge of the bit-line capacitance, which a greater I READ implies.…”

Section: Finfet Application As Inverter and Srammentioning

confidence: 99%