Performance Investigation of Fiber to the Home (FTTH) Ingress Network Based on GPON with Optisystem

Kavitha, T.; Reddy, K. Prabhakar; Sravani, J.

doi:10.1007/978-981-15-5029-4_9

Cited by 8 publications

(2 citation statements)

References 4 publications

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“…1 shows a conventional master slave type flip flop using transmission gate In this design there is drawback of high capacitive clock loading. Due to which there is a higher power consumption even in case of low data activity or static inputs [18]. In Fig.…”

Section: Literature Reviewmentioning

confidence: 99%

Low Power D Flip Flop Design for VLSI Applications

Manikandan¹

2021

JECNAM

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A flip-flop is a basic storage element used to store information. It is used to build RAM, latches, shift registers, counters, and other digital circuits. This paper proposes a new innovative design for D flip-flops. This design consumes much less power than previous flip-flop designs. The first proposed design introduces two gate-leakage transistors at the output gate using the GALEOR method. The second proposed design uses ONOFIC technology. Therefore, compared to the previous design, the power consumption of Design-I and Design-II is reduced by 35.61% and 34.36%, respectively. The proposed design is simulated using a Cadence tool using 90nm CMOS technology operating at 500MHz.

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Section: Literature Reviewmentioning

confidence: 99%

Low Power D Flip Flop Design for VLSI Applications

Manikandan¹

2021

JECNAM

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“…Of the three, memory-based implementations are gaining popularity due to the significant growth of VLSI memory technology.Semiconductor memory is becoming cheaper, faster and consumes less power due to continuous improvements in silicon scaling technology. Advances in memory technology [14][15][16][17][18] have enabled better memory design based on application requirements today, and efficient memory-based multipliers are also possible.In the past, memory was a separate part of the processor unit, but now memory is part of the processor [19][20][21][22]. Since OMS-based multipliers already exist, I wanted to try an efficient OMS-based multiplier design that I hadn't explored and dealt with before.…”

Section: Introductionmentioning

confidence: 99%

Modified Efficient OMS LUT Design for Memory-Based Multiplication

Manikandan¹

2022

JAIMLNN

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This paper proposes an efficient LUT (Look-Up-Table) design called Efficient EOMS (Efficient-OMS Design) for memory-based operations. This proposed design can be used for FPGA implementation as well as ASIC. The proposed design is a better choice than ordinary OMS (Odd Multiplier Store) and is preferred in many DSP calculations where one of the inputs to the filter coefficients is fixed. In this design (N+1), the possible product terms of the input multiplicands with fixed coefficients are stored directly in memory. Doing so allows for a simpler and faster design, unlike the previous proposal OMS (Odd Multiple Storage).Designs that extract odd multiples of the product term can significantly reduce path delay and area complexity with very simple control circuitry. Using (N+1) technology can significantly reduce the area compared to ordinary OMS technology. Additionally, the EOMS technical design is coded in Verilog and simulated and synthesized using Xilinx tools.

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