Performance Investigation of FinFET Structures: Unleashing Multi-Gate Control through Design and Simulation at the 7 nm Technology Node for Next-Generation Electronic Devices

Abstract

We outline a original study that represents the first investigation of its kind, focusing on DC and analog/RF performance of structural flavors of FinFET. A total of six structural variations (D1 to D6 devices) in FinFET as per the IRDS 7 nm technology node specifications is explored. Through extensive simulations, our findings demonstrate that the incorporation of gate stack, spacer, and source/drain extension concepts in FinFETs leads to superior performance. The DC performance analysis produced near-ideal SS (~65mV/dec) performance, lower leakage currents, improved switching performance, and reduced DIBL values for D3 to D6 devices owing to the incorporation of gate stack, spacer integration, and source/drain extension doping. In terms of analog/RF performance, the best suitable device is found to be D4 device having designed with 1017 cm-3 n-type lightly-doped source/drain regions, spacer, and gate stack integrations. A significant improvement such as higher gm, reduced gd, enhanced AV, improved fT, GFP, GTFP, and TFP are obtained for D4 device marking a breakthrough in the FinFET designing. Overall, the findings contribute to the advancement of FinFET at 7 nm technology node, opening up new opportunities for applications in various electronic systems demanding improved device performance.

Optimization of Sidewall Spacer Engineering at Sub-5 nm Technology Node For JL-Nanowire FET: Digital/Analog/RF/Circuit Perspective

“…The Auger recombination model is also employed for accurately capturing the behavior of semiconductor devices at high injection levels, such as in heavily doped regions or under high bias conditions. 30…”