Performance investigations of novel dual-material gate (DMG) MOSFET with dielectric pockets (DP)

Abstract

Dual-material gate MOSFET with dielectric pockets (DMGDP MOSFET) is proposed to eliminate the potential weakness of the DP MOSFET for CMOS scaling toward the 32 nm gate length and beyond. The short-channel effects (SCE) can be effectively suppressed by the insulator near the source/drain regions. And the suppression capability can be even better than the DP MOSFET due to the drain bias absorbed by the screen gate. The speed performance and electronic characteristics of the DMGDP MOSFET are comprehensively studied. Compared to the experimental data from Jurczak et al., the DMGDP PMOSFET exhibits good subthreshold characteristics and the on-state current is almost the twice that of the DP PMOSFET. The intrinsic delay of the NMOS reaches 21% greater than the DP MOSFET for 32 nm node. The higher f T of 390 GHz is achieved, which is a 32% enhancement in comparison with the DP MOSFET when the gate length is 50 nm. Finally, the design guideline and the optimal regions of the DMGDP MOSFET are discussed.dual material gate (DMG), dielectric pockets (DP), short-channel effect (SCE), cutoff frequency

Gate electrode stacked source/drain SON trench MOSFET for biosensing application

“…Also various methods like reactive ion etching, shallow trench isolation (STI) and plasma etching have been suggested for fabrication of recessed channel MOSFET [54]. Similarly different fabrication methods like fully silicide (FUSI), inter diffusion and tilt angle evaporation (TAE) process have been discussed for realization of gate engineering techniques [55,56]. Hence the fabrication of SiGe-DMTG SON MOSFET biosensor may be carried out by implementing the possible fabrication steps that have been already reported in [23,40,56].…”

Linearity-Distortion Analysis of GME-TRC MOSFET for High Performance and Wireless Applications

“…The fabrication of TRC structure is feasible by implementing the fabrication process used by Xiao-Hua et al [16] and Seo et al [17] for grooved gate MOSFET. Further, for GME architecture, many fabrication schemes has been suggested such as inter diffusion process [18,19] and tilt angle evaporation (TAE) [20,21] which makes the fabrication possible even in sub-100 nm regime. Moreover, for the viability of advanced multi-layered gate engineered structures, several techniques [22,23] were reported in the past, using the stack of a thin SiO 2 and a thick high-k layer.…”