Performance Left on the Table: An Evaluation of Compiler Autovectorization for RISC-V

Adit, Neil; Sampson, Adrian

doi:10.1109/mm.2022.3184867

Cited by 10 publications

(2 citation statements)

References 15 publications

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“…Regarding the RISC-V toolchain, we can find studies comparing different RISC-V compilers, such as the work by Poorhosseini et al [11], which examines the performance and size of binaries generated by GCC and LLVM, and compares the performance of the compilers themselves. Other studies, such as the one by Adit and Sampson [12], have focused on compiler auto-vectorization. We observe there is an increasing interest in extending the RISC-V support to compilers, such as the JIT compiler [13].…”

Section: Related Workmentioning

confidence: 99%

RISC-V for Genome Data Analysis: Opportunities and Challenges

López-Villellas,

Pineda-Sánchez,

Badouh

et al. 2023

2023 38th Conference on Design of Circuits and Integrated Systems (DCIS)

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The RISC-V ISA has gained significant momentum in High-Performance Computing (HPC) research and market due to its open-source nature, fostering collaborative research and innovation. The ever-growing RISC-V-based hardware/software ecosystem has made it an attractive option for HPC application development and production. Within the field of biomedical research, genome data analysis has emerged as a crucial step towards personalized medicine, demanding substantial computational resources and more efficient tools.This paper presents a benchmark suite of genome analysis kernels ported to RISC-V and their evaluation on modern RISC-V systems. Our work evaluates the RISC-V toolchain's maturity and the software/hardware ecosystem's readiness for its adoption for genome data analysis. This study aims to provide valuable guidance for researchers and practitioners interested in adopting RISC-V for genome analysis, and provides feedback to the RISC-V community on the challenges that need to be addressed for RISC-V to become an efficient HPC platform.

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Section: Related Workmentioning

confidence: 99%

RISC-V for Genome Data Analysis: Opportunities and Challenges

López-Villellas,

Pineda-Sánchez,

Badouh

et al. 2023

2023 38th Conference on Design of Circuits and Integrated Systems (DCIS)

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“…The SVML instruction set is a short vector math library operation instruction set, allowing programs to call vector versions of functions during vectorization transformation [7]. The vector operation instructions in the V extension instruction set of the RISC-V [8] and the SVE extension instruction set of the ARM [9] are no longer bound to vector lengths [10]. They provide vector length setting instructions, which allows the target platform to support vector operations of different lengths by setting the vector length.…”

Section: Introductionmentioning

confidence: 99%

Loop unrolling optimization for dual SIMD extension

Yao,

Liu,

et al. 2024

Preprint

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SIMD extensions are playing an increasingly important role in high-performance computing and artificial intelligence fields. To fully utilize these components, various manufacturers and institutions have implemented many optimizations for SIMD extensions, with dual SIMD extension pipeline optimization being one of them. This method generates instructions suitable for parallel execution of the integrated dual SIMD extension on processors by unrolling vectorizable loops in programs. It is integrated into a mainstream compiler GCC as an optimization pass and can be enabled with just one compilation option. Experiments were conducted on an SW421 processor, testing standard benchmark suites such as SPEC CPU 2006 and NPB. The experiments showed that after using this optimization pass, programs generated by the compiler can fully utilize the dual SIMD extension during execution. Compared with turning on the autovectorization option, the method has an acceleration effect on multiple applications in the test set, and the execution efficiency is improved by an average of 5.6% and a maximum of 14%.

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