Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling

Tsuchiya, Akira; Hashimoto, Masanori; Onodera, Hidetoshi

doi:10.1093/ietfec/e88-a.4.885

Cited by 8 publications

(8 citation statements)

References 7 publications

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“…In [9], they compare singleended and differential T-Line against conventional buffered RC line in terms of bit rate capacity and energy, and suggested that differential T-Line is the most efficient. In [10], Akira et al studies the tradeoff between bit rate, interconnect length and eye opening for both single-ended and differential TLines. More realistic situation including power/ground noise in designing T-Lines is also considered in [11].…”

Section: Previous Workmentioning

confidence: 99%

Approaching Speed-of-light Distortionless Communication for On-chip Interconnect

Zhu

Shi

Cheng

et al. 2007

2007 Asia and South Pacific Design Automation Conference

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We extend the Surfliner on-chip distortionless transmission line scheme and provide more details for the implementation issues. Surfliner seeks to approach distortionless transmission by intentionally adding shunt resistors between the signal line and the ground. In theory if we distributively make the shunt conductance G=RC/L, there will be no distortion at the receiver end and the signal propagates at the speed of light. We show the feasibility and advantages of this shunt resistor scheme by a real design case of single-ended microstrip line in 0.10µm technology. The simulation results indicate we can achieve near perfect signaling of 10 Gbps data over a 10 mm serial link, yet no pre-emphasis/equalization or other special techniques are needed. Guidelines for determining the optimal value and spacing of the shunt resistors are also provided.

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Section: Previous Workmentioning

confidence: 99%

Approaching Speed-of-light Distortionless Communication for On-chip Interconnect

Zhu

Shi

Cheng

et al. 2007

2007 Asia and South Pacific Design Automation Conference

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“…The fundamental ideas of these techniques require a reduced number of input test patterns rather than lengthy PRBS signals by exploiting creative algorithms [12]- [17] or physical analyses [18]- [23]. Although each technique has its own advantages, they are all considered useful in respective specified applications since they can significantly reduce the required computation time.…”

Section: Introductionmentioning

confidence: 99%

Analytical Eye-Diagram Determination for the Efficient and Accurate Signal Integrity Verification of Single Interconnect Lines

Kim

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In this paper, a new efficient and accurate analytical eye-diagram determination technique for interconnect lines is presented. The simplest input test signal model for the intersymbol interference analysis of high-speed data links is mathematically formulated. Since input test patterns for eye boundaries are determined analytically, it is considered very convenient and efficient. The proposed technique shows excellent agreement with the SPICE-based simulation in both eye height and jitter, i.e., within 5% error for nondiscontinuous data paths and 10% error for discontinuous data paths. The method is much more computation-time-efficient than the pseudorandom bit sequence-based SPICE simulation in the order of magnitude.Index Terms-Eye diagram, intersymbol interference (ISI), jitter, signal integrity, transmission line.

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“…These interconnects are regarded as open-ended transmission-lines because the receiver input is a small capacitance. However to achieve high bit rate signaling over 10 Gbps, resistive termination is required [5]. On the other hand, resistive termination increases the power dissipation because static current flows through the terminator.…”

Section: Introductionmentioning

confidence: 99%

“…We improve the analytical eye-opening estimation in Ref. [5]. Reference [5] provides an analytical performance estimation for only open-ended and impedance matched termination.…”

Section: Introductionmentioning

confidence: 99%

Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling

Tsuchiya¹,

Hashimoto²,

Onodera³

2007

IEICE Transactions on Electronics

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This paper discusses the resistive termination of on-chip high-performance interconnects. Resistive termination is effective to improve the bandwidth of on-chip interconnects, on the other hands, increases the power dissipation and the area. Therefore trade-off analysis about resistive termination is necessary. This paper proposes a method to determine the termination of on-chip interconnects. The termination derived by the proposed method provides minimum sensitivity to process variation as well as maximum eye-opening in voltage.

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Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling

Cited by 8 publications

References 7 publications

Approaching Speed-of-light Distortionless Communication for On-chip Interconnect

Approaching Speed-of-light Distortionless Communication for On-chip Interconnect

Analytical Eye-Diagram Determination for the Efficient and Accurate Signal Integrity Verification of Single Interconnect Lines

Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling

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