Performance measurement of a fully pipelined JPEG codec on emulation platform

Tiwari, Naveen; Reddy, Sagar Chaitanya

doi:10.1109/iadcc.2010.5423018

Cited by 8 publications

(11 citation statements)

References 1 publication

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“…JPEG compression algorithm is very complex and supports different operation modes [1,2]. The professionals in a software and hardware designers implement baseline mode, the one most widely used across the industry [3].…”

Section: Introductionmentioning

confidence: 99%

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Design and Implementation of a Gray Scale JPEG CODEC on Spartan-3E

Salih

Mahmood

2017

Tikrit j. eng. sci.

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This paper presents the design and implementation of the hardware JPEG CODEC for gray scale images. The architecture is designed in a way based on modules that a share between JPEG encoder and decoder circuit. Each module was designed to implement a forward and backward function and they have separate control signals. The JPEG CODEC (Compressor, Decompressor) architecture achieves high throughput with a deep and optimized pipeline, with a target to FPGA device implementation. The designed architectures are detailed in this paper and they are described in VHDL, simulated and physically mapped to XC3S500 FPGAs. The JPEG CODEC pipeline has a minimum latency of 166 clock cycles, that given the full modular pipeline depth. The CODEC could process a 512X 512 pixels still image in 5.2ms, reaching a maximum processing rate of 190 frames per second.

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Section: Introductionmentioning

confidence: 99%

“…In 2007, Tumeo et al [5] designed a JPEG encoder by using Virtex II-Pro XC2VP30, they proposed a mixed HW/SW architecture. Hardware JPEG CODEC was synthesized for Xilinx Virtex-II FPGA device on ARM926EJS emulation base board which can operate at frequencies up to 6MHz [2].…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of a Gray Scale JPEG CODEC on Spartan-3E

Salih

Mahmood

2017

Tikrit j. eng. sci.

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“…Large number of high quality color images used in many multimedia applications, requires high capacity mass storage devices. JPEG, whose encoding starts with RGB to YCbCr conversion has become the most popular image compression technique and is the best example where such conversion is used [5,6]. Moreover this conversion is also needed in many video designs, digital coding of TV pictures, HIDTV and video digital libraries [7].…”

Section: Introductionmentioning

confidence: 99%

Implementation of Multiplier less Architectures for Color Space Conversions on FPGA

Mahmood¹,

Salih²

2011

(AREJ)

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The divergence of computers, internet, and wide variety of interactive video devices, in most of the multimedia applications, all using different color representations, is forcing the digital designer today to convert between them. The objective is to have a converter, which will be useful for number of applications with a basic function of converting from one color space to another and the inverse on same architecture. This paper presents an efficient parallel multiplierless implementation for two color space converters (RGB to YCbCr and YCbCr to RGB). The proposed architecture is based on distributed arithmetic (DA) principles which has been implemented on the Xilinx Spartan-3E XC3S500 FPGA using fewer resources. The implementation approach exhibits better performances when compared with existing implementations, Modifications have been carried out in DA to reduce the hardware complexity with better performance in area, latency and throughput.

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“…In 2007, Tumeo et al [5] designed a JPEG encoder by using Virtex II-Pro XC2VP30, they proposed a mixed HW/SW architecture. Hardware JPEG CODEC was synthesized for Xilinx Virtex-II FPGA device on ARM926EJS emulation base board, it can operate at frequencies up to 6MHz [2].…”

Section: Introductionmentioning

confidence: 99%

“…JPEG compression algorithm is very complex and supports different operation modes [1,2]. Software professionals and hardware designers implement baseline mode, the one most widely used across the industry [3].…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Gray Scale JPEG CODEC on Spartan-3E

Salih¹,

Mahmood²

2017

Tikrit j. eng. sci.

View full text Add to dashboard Cite

This paper presents the design and implementation of the hardware JPEG CODEC for gray scale images. The architecture is designed in a way based on modules, all modules are sharing between JPEG encoder and decoder circuit . Each module was designed to implement forward and backward function and they have separate control signals. The JPEG CODEC (Compressor, Decompressor) architecture achieves high throughput with a deep and optimized pipeline, with a target to FPGA device implementation. The designed architectures are detailed in this paper and they were described in VHDL, simulated and physically mapped to XC3S500 FPGAs. The JPEG CODEC pipeline has a minimum latency of 166 clock cycles, given the full modular pipeline depth. The CODEC can process a 512X 512 pixels still image in 5.2ms, reaching a maximum processing rate of 190 frames per second.

show abstract

Performance measurement of a fully pipelined JPEG codec on emulation platform

Cited by 8 publications

References 1 publication

Design and Implementation of a Gray Scale JPEG CODEC on Spartan-3E

Design and Implementation of a Gray Scale JPEG CODEC on Spartan-3E

Implementation of Multiplier less Architectures for Color Space Conversions on FPGA

Design and Implementation of Gray Scale JPEG CODEC on Spartan-3E

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