Performance Modelling and Dynamic Scheduling on Heterogeneous-ISA Multi-core Architectures

Boran, Nirmal Kumar; Yadav, Dinesh Kumar; Iyer, Rishabh

doi:10.1007/978-981-32-9767-8_58

Cited by 4 publications

(3 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

Section: Methodsmentioning

confidence: 99%

“…Nonetheless, it is important to note that the performance counters of a compute kernel are tied to its performance characteristics and are a very good predictor of its future performance. 43,44 Therefore, it is not required to run the whole program to get a good picture of the behavior of one compute kernel. In other words, it is possible to get the performance counters needed for performance analysis using a simple example of the target compute kernel.…”

Section: Performance Countersmentioning

confidence: 99%

See 1 more Smart Citation

Visualization of profiling and tracing in CPU‐GPU programs

Fiorini

Dagenais

2022

Concurrency and Computation

View full text Add to dashboard Cite

Summary As the complexity of the toolchain increases for heterogeneous CPU‐GPU systems, the needs for comprehensive tracing and debugging tools also grows. Heterogeneous platforms bring new possibilities but also new performance issues that are hard to detect. Some techniques that were used on CPU programs are now adapted to GPUs. However, there are some concepts specific to GPUs, like SIMD processing, and the effects of the close interactions between the CPUs and the GPUs, with shared virtual memory and user‐level queues. Multiple sources of data need to be extracted and correlated to obtain a more global view of the performance. In this article, we introduce a novel approach for measuring and visualizing performance defects inside CPU‐GPU programs by combining kernel events, compute kernel events, user API calls and memory transfers. We created two new views that combine this information, to help provide a global view. This framework uses the open source user queue system described in the HSA standard. It can easily be adapted to any user queue system for heterogeneous computing devices. We compare this framework with current existing tools and test it against the Rodinia benchmark. We look at how the execution behavior affects the tracing and profiling overhead and we use Trace Compass to visualize the resulting trace.

show abstract

Section: Methodsmentioning

confidence: 99%

Section: Performance Countersmentioning

confidence: 99%

Visualization of profiling and tracing in CPU‐GPU programs

Fiorini

Dagenais

2022

Concurrency and Computation

View full text Add to dashboard Cite

show abstract

“…We were heavily inspired by more recent work on performance modeling of both software [15,16,24,25,30,31,38,52,56,64,65] and hardware [9,10,19,20,27,28,37]. In particular, we borrowed the notion of performance interfaces as programs from PIX [30] and Freud [56], although both use such interfaces for software running on general-purpose hardware and neither can reason about throughput.…”

Section: Related Workmentioning

confidence: 99%

The Case for Performance Interfaces for Hardware Accelerators

Iyer

Argyraki

et al. 2023

Proceedings of the 19th Workshop on Hot Topics in Operating Systems

View full text Add to dashboard Cite

While systems designers are increasingly turning to hardware accelerators for performance gains, realizing these gains is painstaking and error-prone. It can take several person-months to determine if a given accelerator is a good fit for a given piece of code, and accelerators that cost millions of dollars to build can slow down the very systems they were designed to accelerate.We argue that hardware accelerators must come with performance interfaces-interfaces that provide usable information about the accelerator's performance behavior just like semantic interfaces do for functionality-to facilitate their correct use. Since accelerators do not provide new functionality and are only useful if they improve system performance, performance interfaces are as integral to their correct use as semantic interfaces.

show abstract