Performance of the Final Event Builder for the ATLAS Experiment

Beck, H. P.; Abolins, M.; Battaglia, A.; Blair, R. E.; Bogaerts, A.; Bosman, M.; Ciobotaru, M. D.; Cranfield, R.; Crone, G.; Dawson, J. W.; Dobinson, R.; Dobson, M.; Anjos, A. Dos; Drake, G.; Ermoline, Y.; Ferrari, R.; Ferrer, M. L.; Francis, D.; Gadomski, S.; Gameiro, S.; Gorini, B.; Green, B.; Haberichter, W.; Häberli, Christian; Hauser, R.; Hinkelbein, C.; Hughes-Jones, R. E.; Joos, M.; Kieft, G.; Klous, S.; Korcyl, K.; Kordas, K.; Kugel, A.; Leahu, L.; Lehmann, G.; Martin, B.; Mapelli, L.; Meessen, C.; Meiroşu, Cătălin; Misiejuk, A.; Mornacchi, G.; Müller, Matthias; Nagasaka, Y.; Negri, A.; Pauly, T.; Petersen, J.; Pope, B. G.; Schlereth, J. L.; Spiwoks, R.; Stancu, S.; Strong, J. A.; Sushkov, S.; Szymocha, T.; Tremblet, L.; Ünel, G.; Vandelli, W.; Vermeulen, J. C.; Werner, P.; Wheeler-Ellis, S. J.; Wickens, F. J.; Wiedenmann, W.; Yu, Maoyuan; Yasu, Y.; Zhang, Jinlong; Zobernig, H.

doi:10.1109/tns.2007.910868

Cited by 8 publications

(5 citation statements)

References 6 publications

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“…Therefore and as detailed in ref. [71], the SFI implements network traffic shaping (the number of outstanding requests cannot be larger than a certain maximum, which typically is 10), 7This can be achieved with the help of the TTC2LAN application. This application runs on the single board computer of each TTC crate containing a "master" Local Trigger Processor (LTP) [9], i.e.…”

Section: The Sfimentioning

confidence: 99%

The ATLAS Data Acquisition and High Level Trigger system

2016

J. Inst.

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Section: The Sfimentioning

confidence: 99%

The ATLAS Data Acquisition and High Level Trigger system

2016

J. Inst.

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“…For Run 2, the separate L2 and EF farms were combined into a single, homogeneous HLT farm [31]. During Run 1, Level 2 requested only partial event data to be sent over the network, while the event filter operated on the full event information assembled by separate farm nodes dedicated to event building [32]. For Run 2, merging the separate farms into a single homogeneous farm allowed for better resource sharing and an overall simplification of both the hardware and software.…”

Section: The Atlas Detector Trigger and Data Acquisition Systemsmentioning

confidence: 99%

The ATLAS inner detector trigger performance in pp collisions at 13 TeV during LHC Run 2

Aad

Abbott²,

Abbott³

et al. 2022

Eur. Phys. J. C

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The design and performance of the inner detector trigger for the high level trigger of the ATLAS experiment at the Large Hadron Collider during the 2016–2018 data taking period is discussed. In 2016, 2017, and 2018 the ATLAS detector recorded $$35.6~\mathrm {fb}^{-1}$$ 35.6 fb - 1 , $$46.9~\mathrm {fb}^{-1}$$ 46.9 fb - 1 , and $$60.6~\mathrm {fb}^{-1}$$ 60.6 fb - 1 respectively of proton–proton collision data at a centre-of-mass energy of 13 TeV. In order to deal with the very high interaction multiplicities per bunch crossing expected with the 13 TeV collisions the inner detector trigger was redesigned during the long shutdown of the Large Hadron Collider from 2013 until 2015. An overview of these developments is provided and the performance of the tracking in the trigger for the muon, electron, tau and b-jet signatures is discussed. The high performance of the inner detector trigger with these extreme interaction multiplicities demonstrates how the inner detector tracking continues to lie at the heart of the trigger performance and is essential in enabling the ATLAS physics programme.

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“…ARM SoCs also have potential application in higher level triggering and reconstruction systems. The synthetic performance benchmarks indicate that ARM SoC performance is similar to the Intel and AMD CPUs currently in use in the Event Builder, for example [6]. In order to pursue this line of investigation, the ATLAS software would have to be recompiled for the ARM instruction set which will be a significant and challenging undertaking.…”

Section: Data Throughput Testingmentioning

confidence: 99%

The development of a general purpose ARM-based processing unit for the ATLAS TileCal sROD

Cox

Reed²,

Mellado

2015

J. Inst.

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The Large Hadron Collider at CERN generates enormous amounts of raw data which present a serious computing challenge. After Phase-II upgrades in 2022, the data output from the ATLAS Tile Calorimeter will increase by 200 times to 41 Tb/s! ARM processors are common in mobile devices due to their low cost, low energy consumption and high performance. It is proposed that a cost-effective, high data throughput Processing Unit (PU) can be developed by using several consumer ARM processors in a cluster configuration to allow aggregated processing performance and data throughput while maintaining minimal software design difficulty for the end-user. This PU could be used for a variety of high-level functions on the high-throughput raw data such as spectral analysis and histograms to detect possible issues in the detector at a low level. High-throughput I/O interfaces are not typical in consumer ARM System on Chips but high data throughput capabilities are feasible via the novel use of PCI-Express as the I/O interface to the ARM processors. An overview of the PU is given and the results for performance and throughput testing of four different ARM Cortex System on Chips are presented.

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Performance of the Final Event Builder for the ATLAS Experiment

Cited by 8 publications

References 6 publications

The ATLAS Data Acquisition and High Level Trigger system

The ATLAS Data Acquisition and High Level Trigger system

The ATLAS inner detector trigger performance in pp collisions at 13 TeV during LHC Run 2

The development of a general purpose ARM-based processing unit for the ATLAS TileCal sROD

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