Performance of the full field EUV systems

Meiling, H.; Boon, Edwin; Buzing, Nico; Cummings, K. D.; Frijns, Olav; Galloway, Judy; Goethals, M.; Harned, Noreen; Hultermans, Bas; Jonge, Roel de; Kessels, Bart; Kürz, P.; Lok, Sjoerd; Lowisch, Martin; Mallman, Joerg; Pierson, Bill; Ronse, Kurt G.; Ryan, J.; Smitt-Weaver, Emil; Tittnich, Michael; Wagner, Christian; Dijk, Andre van; Zimmerman, John

doi:10.1117/12.773259

Cited by 22 publications

(12 citation statements)

References 4 publications

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“…The flare level in the three different regions was set by using various densities for the dummy fill. For the low, mid and high flare region a wafer flare value of 4.3%, 6.3% and 8.3% was calculated based on the PSF provided by tool manufacturer [6]. Note that we use a flare TIS value of 20% which needs to be normalized by the multi layer reflectivity by definition, corresponding to an effective TIS value of ~ 14.4 %.…”

Section: Pattern Set Used For Calibrationmentioning

confidence: 99%

Physical resist models and their calibration: their readiness for accurate EUV lithography simulation

et al. 2010

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In this paper, we discuss the performance of EUV resist models in terms of predictive accuracy, and we assess the readiness of the corresponding model calibration methodology. The study is done on an extensive OPC data set collected at IMEC for the ShinEtsu resist SEVR-59 on the ASML EUV Alpha Demo Tool (ADT), with the data set including more than thousand CD values. We address practical aspects such as the speed of calibration and selection of calibration patterns. The model is calibrated on 12 process window data series varying in pattern width (32, 36, 40 nm), orientation (H, V) and pitch (dense, isolated). The minimum measured feature size at nominal process condition is a 32 nm CD at a dense pitch of 64 nm. Mask metrology is applied to verify and eventually correct nominal width of the drawn CD. Crosssectional SEM information is included in the calibration to tune the simulated resist loss and sidewall angle. The achieved calibration RMS is ~ 1.0 nm. We show what elements are important to obtain a well calibrated model. We discuss the impact of 3D mask effects on the Bossung tilt. We demonstrate that a correct representation of the flare level during the calibration is important to achieve a high predictability at various flare conditions. Although the model calibration is performed on a limited subset of the measurement data (one dimensional structures only), its accuracy is validated based on a large number of OPC patterns (at nominal dose and focus conditions) not included in the calibration; validation RMS results as small as 1 nm can be reached. Furthermore, we study the model's extendibility to two-dimensional end of line (EOL) structures. Finally, we correlate the experimentally observed fingerprint of the CD uniformity to a model, where EUV tool specific signatures are taken into account.

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Section: Pattern Set Used For Calibrationmentioning

confidence: 99%

Physical resist models and their calibration: their readiness for accurate EUV lithography simulation

et al. 2010

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“…IMEC has recently installed one of the very first EUV full-field tools. This ASML Alpha Demo Tool (EUV ADT) is providing important learning to the industry on the implementation of EUV lithography in silicon processing ( Figure 2) [7,8]. …”

Section: Lithography Tool and Process Optionsmentioning

confidence: 99%

Lithography options and challenges for sub-45nm node interconnect layers

Maenhoudt

2008

2008 International Interconnect Technology Conference

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“…In 2010 ASML has started the shipments of the second generation EUV system, the NXE:3100, to customers around the world and covering all main lithographic segments (DRAM, FLASH, LOGIC, MPU) [1,2,10] Both the ADT and the NXE:3100 system utilize optics with an NA of 0.25. Now more than 30000 wafers have been exposed [see Figure 1] on the NXE:3100 and at multiple public occurrences customers have presented the results obtained with both systems showing good imaging and overlay performance.…”

Section: Introductionmentioning

confidence: 99%

ASML's NXE platform performance and volume introduction

Peeters

Lok

Alphen

et al. 2013

Extreme Ultraviolet (EUV) Lithography IV

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All six NXE:3100, 0.25 NA EUV exposure systems are in use at customer sites enabling device development and cycles of learning for early production work in all lithographic segments; Logic, DRAM, MPU, and FLASH memory. NXE EUV lithography has demonstrated imaging and overlay performance both at ASML and end-users that supports sub27nm device work. Dedicated chuck overlay performance of <2nm has been shown on all six NXE:3100 systems.The key remaining challenge is productivity, which translates to a cost-effective introduction of EUVL in high-volume manufacturing (HVM). High volume manufacturing of the devices and processes in development is expected to be done with the third generation EUV scanners -the NXE:3300B. The NXE:3300B utilizes an NA of 0.33 and is positioned at a resolution of 22nm which can be extended to 18nm with off-axis illumination. The subsystem performance is improved to support these imaging resolutions and overall productivity enhancements are integrated into the NXE platform consistent with 125 wph. Since EUV reticles currently do not use a pellicle, special attention is given to reticle-addeddefects performance in terms of system design and machine build including maintenance procedures.In this paper we will summarize key lithographic performance of the NXE:3100 and the NXE:3300B, the NXE platform improvements made from learning on NXE:3100 and the Alpha Demo Tool, current status of EUV sources and development for the high-power sources needed for HVM.Finally, the possibilities for EUV roadmap extension will be reviewed.

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Performance of the full field EUV systems

Cited by 22 publications

References 4 publications

Physical resist models and their calibration: their readiness for accurate EUV lithography simulation

Physical resist models and their calibration: their readiness for accurate EUV lithography simulation

Lithography options and challenges for sub-45nm node interconnect layers

ASML's NXE platform performance and volume introduction

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