Performance Optimization and FPGA Implementation of Real-Time Tone Mapping

Popović, Vladan; Pignat, E.; Leblebici, Yusuf

doi:10.1109/tcsii.2014.2345306

Cited by 23 publications

(10 citation statements)

References 17 publications

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“…Obviously, there is trade-off among latency, resources and quality of the output. For calculation of average and SD in PL, Popovic et al [43] assumed the no variation of light between two frames in a sequence. If we adopt this method in our case, we may need assumption that light is constant among four frames in a sequence because we need three frames in a sequence to calculate the third, fourth, and fifth blocks of PS side in Figure 6.…”

Section: Hls Developmentmentioning

confidence: 99%

HLS Based Approach to Develop an Implementable HDR Algorithm

Saha¹,

Banik²,

Kim³

2018

Electronics

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Hardware suitability of an algorithm can only be verified when the algorithm is actually implemented in the hardware. By hardware, we indicate system on chip (SoC) where both processor and field-programmable gate array (FPGA) are available. Our goal is to develop a simple algorithm that can be implemented on hardware where high-level synthesis (HLS) will reduce the tiresome work of manual hardware description language (HDL) optimization. We propose an algorithm to achieve high dynamic range (HDR) image from a single low dynamic range (LDR) image. We use highlight removal technique for this purpose. Our target is to develop parameter free simple algorithm that can be easily implemented on hardware. For this purpose, we use statistical information of the image. While software development is verified with state of the art, the HLS approach confirms that the proposed algorithm is implementable to hardware. The performance of the algorithm is measured using four no-reference metrics. According to the measurement of the structural similarity (SSIM) index metric and peak signal-to-noise ratio (PSNR), hardware simulated output is at least 98.87 percent and 39.90 dB similar to the software simulated output. Our approach is novel and effective in the development of hardware implementable HDR algorithm from a single LDR image using the HLS tool.

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Section: Hls Developmentmentioning

confidence: 99%

HLS Based Approach to Develop an Implementable HDR Algorithm

Saha¹,

Banik²,

Kim³

2018

Electronics

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“…The developed FPGA-based processing system is able to reconstruct the HDR frame using the proposed method and tone map the resulting image using a hardware-adapted global operator. Detailed explanation of the implementation of the HDR Panoptic System can be seen in [39] and [40].…”

Section: A Real-time Hdr Panorama With Panoptic Cameramentioning

confidence: 99%

“…Hence, we adopted the parameters to relax the hardware implementation, without losing any image quality. In [40], the new tone mapping operator suitable for hardware implementation is described in detail. The set of required mathematical operations is reduced to only addition, multiplication and division, which are suitable for fast implementation.…”

Section: Tone Mappingmentioning

confidence: 99%

Real-Time Omnidirectional Imaging System with Interconnected Network of Cameras

Seyid

Cogal

Popović

et al. 2015

VLSI-SoC: Internet of Things Foundations

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International audienceThe Panoptic camera is an omnidirectional multi-aperture visual system which is realized by mounting multiple imaging sensors on a hemispherical frame. In this chapter, we will present a novel distributed and parallel implementation of the real-time omnidirectional vision reconstruction algorithm of the Panoptic Camera, for camera modules with processing, memory and interconnectivity features. A methodology for the arrangement of camera modules with interconnectivity feature into a target interconnection network topology will be introduced. A unique custom-made multiple-FPGA hardware platform designed for the implementation of an interconnected network of a 49 camera prototype Panoptic system will be explained. A novel way to represent the omnidirectional data obtained from the Panoptic Camera and real-time high dynamic range (HDR) video application which is realized by the system will be presented

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“…Reference [ 15 ] proposed a Tone Mapping processor combining a global compression model and a local contrast enhancement model for each pixel to perform tone mapping. Reference [ 16 ] proposed an optimized global tone mapping processor based on the drago operator [ 17 ] for high precision image processing. Reference [ 18 ] summarize and categorize the state-of-the-art research in tone mapping.…”

Section: Introductionmentioning

confidence: 99%

A Biological Retina Inspired Tone Mapping Processor for High-Speed and Energy-Efficient Image Enhancement

Xiang

Liu

Que

et al. 2020

Sensors

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In this work, a biological retina inspired tone mapping processor for high-speed and energy-efficient image enhancement has been proposed. To achieve high throughput and high energy efficiency, several hardware design techniques have been proposed, including data partition based parallel processing with S-shape sliding, adjacent frame feature sharing, multi-layer convolution pipelining, and convolution filter compression with zero skipping convolution. Implemented on a Xilinx’s Virtex7 FPGA, the proposed design achieves a high throughput of 189 frames per second for 1024 × 768 RGB images while consuming 819 mW. Compared with several state-of-the-art tone mapping processors, the proposed design shows higher throughput and energy efficiency. It is suitable for high-speed and energy-constrained image enhancement applications.

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Performance Optimization and FPGA Implementation of Real-Time Tone Mapping

Cited by 23 publications

References 17 publications

HLS Based Approach to Develop an Implementable HDR Algorithm

HLS Based Approach to Develop an Implementable HDR Algorithm

Real-Time Omnidirectional Imaging System with Interconnected Network of Cameras

A Biological Retina Inspired Tone Mapping Processor for High-Speed and Energy-Efficient Image Enhancement

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