Performance Optimization of Aho-Corasick Algorithm on a GPU

Tran, Nhat-Phuong; Lee, Myungho; Hong, Sugwon; Bae, Jongwoo

doi:10.1109/trustcom.2013.138

Cited by 10 publications

(7 citation statements)

References 12 publications

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“…Besides the DFA partitioning based parallelization approach described above, we apply further performance optimization techniques to our GPU implementation. They are mostly taken from our earlier work [15].…”

Section: Further Performance Optimizationsmentioning

confidence: 99%

“…While loading a data block, we let multiple threads generate memory access which fall within the 128-bytes range so that these access get combined into one request and sent to the memory [10]. This saves the memory bandwidth a lot and improves the performance [15].…”

Section: Further Performance Optimizationsmentioning

confidence: 99%

“…We use a store scheme through which a chunk of data loaded from the global memory gets divided up into 4-bytes units and stored in the shared memory at the addresses which are mapped to the consecutive shared memory banks in a diagonal way. This store scheme avoids any bank conflicts and results in a conflict-free load from the shared memory banks [15]. (iii) The GPU is executing in multithreaded fashion.…”

Section: Scientific Programmingmentioning

confidence: 99%

“…Therefore, finding an optimal number of threads to effectively hide the off-chip memory latencies while efficiently utilizing the large number of thread processor cores and the memory bandwidth is crucial for obtaining high performance. We attempt to find and schedule an optimal number of parallel threads onto the hardware thread blocks and the thread processor cores by almost exhaustively searching various input chunk sizes to be assigned to each thread [15].…”

Section: Scientific Programmingmentioning

confidence: 99%

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Cache Locality-Centric Parallel String Matching on Many-Core Accelerator Chips

Tran

Lee

Choi

2015

Scientific Programming

Self Cite

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Aho-Corasick (AC) algorithm is a multiple patterns string matching algorithm commonly used in computer and network security and bioinformatics, among many others. In order to meet the highly demanding computational requirements imposed on these applications, achieving high performance for the AC algorithm is crucial. In this paper, we present a high performance parallelization of the AC on the many-core accelerator chips such as the Graphic Processing Unit (GPU) from Nvidia and the Intel Xeon Phi. Our parallelization approach significantly improves the cache locality of the AC by partitioning a given set of string patterns into multiple smaller sets of patterns in a space-efficient way. Using the multiple pattern sets, intensive pattern matching operations are concurrently conducted with respect to the whole input text data. Compared with the previous approaches where the input data is partitioned amongst multiple threads instead of partitioning the pattern set, our approach significantly improves the performance. Experimental results show that our approach leads up to 2.73 times speedup on the Nvidia K20 GPU and 2.00 times speedup on the Intel Xeon Phi compared with the previous approach. Our parallel implementation delivers up to 693 Gbps throughput performance on the K20.

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Section: Further Performance Optimizationsmentioning

confidence: 99%

Section: Further Performance Optimizationsmentioning

confidence: 99%

Section: Scientific Programmingmentioning

confidence: 99%

Section: Scientific Programmingmentioning

confidence: 99%

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Cache Locality-Centric Parallel String Matching on Many-Core Accelerator Chips

Tran

Lee

Choi

2015

Scientific Programming

Self Cite

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“…To identify the existence of malicious signatures in the packet payload, various pattern-matching algorithms were used. Pattern matching is a computationally intensive task that accounts for up to 75% of the execution time of IDSs [6]. There is no dependency between instructions in signature matching.…”

Section: Figurementioning

confidence: 99%

Network Traffic Anomaly-Detection Framework Using GPUs

Ramesh

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NETWORK TRAFFIC ANOMALY-DETECTION FRAMEWORK USING GPUS by Meera Ramesh Network security has been very crucial for the software industry. Deep packet inspection (DPI) is one of the widely used approaches in enforcing network security. Due to the high volume of network traffic, it is challenging to achieve high performance for DPI in real time. In this thesis, a new DPI framework is presented that accelerates packet header checking and payload inspection on graphics processing units (GPUs). Various optimizations were applied to GPU-version packet inspection, such as thread-level and block-level packet assignment, warp divergence elimination, and memory transfer optimization using pinned memory and shared memory. The performance of the pattern-matching algorithms used for DPI was analyzed by using an assorted set of characteristics such as pipeline stalls, shared memory efficiency, warp efficiency, issue slot utilization, and cache hits. The extensive characterization of the algorithms on the GPU architecture and the performance comparison among parallel pattern-matching algorithms on both the GPU and the CPU are the unique contributions of this thesis. Among the GPU-version algorithms, the Aho-Corasick algorithm and the Wu-Manber algorithm outperformed the Rabin-Karp algorithm because the Aho-Corasick and the Wu-Manber algorithms were executed only once for multiple signatures by using the tables generated before the searching phase was begun. According to my evaluation on a NVIDIA K80 GPU, the GPU-accelerated packet processing achieved at least 60 times better performance than CPU-version processing. ACKNOWLEDGMENTS It is with immense gratitude that I acknowledge the support of my advisor Dr. Hyeran Jeon throughout the thesis. Prof. Hyeran is one of the best Professors I've met and I've learned many things from her, the most important quality I cultivated because of her is patience. I would also like to thank my co-advisor Dr. Younghee Park for monitoring the progress of the project and for providing me good ideas to solve certain issues I had faced. I am also very thankful to Dr. Xiao Su for being a part of the committee and for providing her advice on the future scope of the thesis. I am indebted to my parents and my brother for instilling confidence in me. I'm thankful to my in-laws for their constant support and motivation. I'm also thankful to my friend Sindhuja, who gave her ear to my problems. This thesis would have remained a dream had it not been for the support from my husband Karthik, and I owe my deepest gratitude to him. v TABLE OF CONTENTS List of Tables .

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A Framework of Signature-Matching-Algorithms for IoT Intrusion Detection

Domb

2020

Advances in Intelligent Systems and Computing

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Performance Optimization of Aho-Corasick Algorithm on a GPU

Cited by 10 publications

References 12 publications

Cache Locality-Centric Parallel String Matching on Many-Core Accelerator Chips

Cache Locality-Centric Parallel String Matching on Many-Core Accelerator Chips

Network Traffic Anomaly-Detection Framework Using GPUs

A Framework of Signature-Matching-Algorithms for IoT Intrusion Detection

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