Performance optimization of an FPGA-based configurable multiprocessor for matrix operations

Wang, Xiaofang; Ziavras, Sotirios G.

doi:10.1109/fpt.2003.1275763

Cited by 11 publications

(1 citation statement)

References 7 publications

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“…The use of FPGAs in control systems applications has shown remarkable changes in the last decade, moving from a co-processor approach [49,61,53] to a full system on chip approach [14,45,32]. Initial results found in [10,51,50,59] indicate a speed up in the order of 10 × -1000× times when compared to other technologies.…”

Section: Introductionmentioning

confidence: 98%

Automatic parallelisation for LTI MIMO state space systems using FPGAs. An optimisation for cost & performance

Apopei¹,

Dodd²

2012

Journal of Parallel and Distributed Computing

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Section: Introductionmentioning

confidence: 98%

Automatic parallelisation for LTI MIMO state space systems using FPGAs. An optimisation for cost & performance

Apopei¹,

Dodd²

2012

Journal of Parallel and Distributed Computing

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Efficient hardware support for pattern matching in network intrusion detection

Guinde

Ziavras

2010

Computers & Security

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Abstract-Deep packet inspection forms the backbone of any Network Intrusion Detection (NID) system. It involves matching known malicious patterns against the incoming traffic payload. Pattern matching in software is prohibitively slow in comparison to current network speeds. Due to the high complexity of matching, only FPGA (Field-Programmable Gate Array) or ASIC (Application-Specific Integrated Circuit) platforms can provide efficient solutions. FPGAs facilitate target architecture specialization due to their field programmability. Costly ASIC designs, on the other hand, are normally resilient to pattern updates. Our FPGA-based solution performs high-speed pattern matching while permitting pattern updates without resource reconfiguration. To its advantage, our solution can be adopted by software and ASIC realizations, however at the expense of much lower performance and higher price, respectively. Our solution permits the NID system to function while pattern updates occur. An off-line optimization method first finds common subpatterns across all the patterns in the SNORT database of signatures [14]. A novel technique then compresses each pattern into a bit vector, where each bit represents such a sub-pattern. This approach reduces drastically the required on-chip storage as well as the complexity of pattern matching. The bit vectors for newly discovered patterns can be generated easily using a simple high-level language program before storing them into the on-chip RAM. Compared to earlier approaches, not only is our strategy very efficient while supporting runtime updates but it also results in impressive area savings; it utilizes just 0.052 logic cells for processing and 17.77 bits for storage per character in the current SNORT database of 6455 patterns. Also, the total number of logic cells for processing the traffic payload does not change with pattern updates.

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Coprocessor design to support MPI primitives in configurable multiprocessors

2007

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The Message Passing Interface (MPI) is a widely used standard for interprocessor communications in parallel computers and PC clusters. Its functions are normally implemented in software due to their enormity and complexity, thus resulting in large communication latencies. Limited hardware support for MPI is sometimes available in expensive systems. Reconfigurable computing has recently reached rewarding levels that enable the embedding of programmable parallel systems of respectable size inside one or more FieldProgrammable Gate Arrays (FPGAs). Nevertheless, specialized components must be built to support interprocessor communications in these FPGA-based designs, and the resulting code may be difficult to port to other reconfigurable platforms. In addition, performance comparison with conventional parallel computers and PC clusters is very cumbersome or impossible since the latter often employ MPI or similar communication libraries. The introduction of a hardware design to implement directly MPI primitives in configurable multiprocessor computing creates a framework for efficient parallel code development involving data exchanges independently of the underlying hardware implementation. This process also supports the portability of MPI-based code developed for more conventional platforms. This paper takes advantage of the effectiveness and efficiency of one-sided Remote Memory Access (RMA) communications, and presents the design and evaluation of a coprocessor that implements a set of MPI primitives for RMA. These primitives form a universal and orthogonal set that can be used to implement any other MPI function. To evaluate the coprocessor, a router of low latency was designed as well to enable the direct interconnection of several coprocessors in cluster-on-a-chip systems. Experimental results justify the implementation of the MPI primitives in hardware to support parallel programming in reconfigurable computing. Under continuous traffic, results for a Xilinx XC2V6000 FPGA show that the average transmission time per 32-bit word is about 1.35 clock cycles. Although other computing platforms, such as PC clusters, could benefit as well from our design methodology, our focus is exclusively reconfigurable multiprocessing that has recently received tremendous attention in academia and industry. r

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Performance optimization of an FPGA-based configurable multiprocessor for matrix operations

Abstract: Abstract

Cited by 11 publications

References 7 publications

Automatic parallelisation for LTI MIMO state space systems using FPGAs. An optimisation for cost & performance

Automatic parallelisation for LTI MIMO state space systems using FPGAs. An optimisation for cost & performance

Efficient hardware support for pattern matching in network intrusion detection

Coprocessor design to support MPI primitives in configurable multiprocessors

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