Performance optimization of VLSI interconnect layout

Cong, Jason; He, Lei; Koh, Cheng-Kok; Madden, Patrick H.

doi:10.1016/s0167-9260(96)00008-9

Cited by 282 publications

(185 citation statements)

References 47 publications

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“…It was shown that the Elmore delay model offers reasonably good fidelity for interconnect layout optimization, i.e., an optimal or near-optimal solution obtained under the Elmore delay model is also close to optimal according to actual (SPICE-computed) delays (see [3] for details). But the absolute value of Elmore delay may not be very accurate.…”

Section: A Interconnect Modelingmentioning

confidence: 99%

“…Due to the page limitation, the authors are able to present only a small subset of results on the topics covered in this paper. A more comprehensive survey and bibliography is available in [3].…”

Section: B Fmentioning

confidence: 99%

“…Moments of an RC tree can be computed efficiently using recursive methods (see [3] for details). The first moment £ c o n y R p t w C x y 0 m r y , also called the Elmore delay model [4], is most commonly used for delay estimation in an RC tree.…”

Section: A Interconnect Modelingmentioning

confidence: 99%

“…It is difficult, however, to represent the poles and residues in x h explicitly in terms of design parameters of the interconnect in a closed-form expression, which makes the moment-matching method difficult to use for interconnect optimization directly . Some delay metrics based on higher order moments, such as the central moments and the explicit RC delay using the first three moments, are summarized in [3]. Note that except for the Elmore delay model, which is defined for a monotonic response only, the techniques presented above still holds when interconnects are modeled as RLC trees.…”

Section: A Interconnect Modelingmentioning

confidence: 99%

“…The commonly used methods include iterative addition of Steiner points, optimal merging of edges of a minimum spanning tree (MST), or iterative refinement of an MST. These methods are surveyed in [3]. However, when the interconnect resistance needs to be considered as well, wirelength minimization alone during global routing may not lead to the minimum interconnect delay.…”

Section: A Wirelength Minimizationmentioning

confidence: 99%

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Interconnect design for deep submicron ICs

Cong

Pan

et al. 1997

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97

126

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I. INTERCONNECT TRENDS AND CHALLENGESThe driving force behind the impressive advancement of the VLSI circuit technology has been the rapid scaling of the feature size, i.e., the minimum dimension of the transistor. Table I lists the main characteristics of each technology generation in the NTRS. Such rapid scaling has two profound impacts. First, it enables much higher degree of on-chip integration. The number of transistors per chip will increase by more than 2 per generation to reach 800 millions in the© ¢ m technology. Second, it implies that the circuit performance will be increasingly determined by the interconnect performance. The interconnect design will play the most critical role in achieving the projected clock frequencies in the NTRS. This paper presents the trends and challenges of interconnect design in current and future technologies and discusses the available solutions.In order to better understand the significance of interconnect design in the future technology generations, we performed a number of experiments based on the interconnect parameters provided in the NTRS as shown in the bold face in Table II global interconnects, we also derived the interconnect parameters for the M4 layer,c which are also shown in Table II. Furthermore, we derived a set of device parameters as shown in Table III based on the data on processes and device in the NTRS. Using these sets of parameters, we carried out extensive simulations using HSPICE to quantitatively measure the interconnect performance and reliability in future technology generations and obtained the following results:(1) Interconnect delay is clearly the dominating factor in determincWe assume that the minimum width and spacing of M4 is 2.5 times those of M1. The aspect ratios 7 6 8 and 7 6 A @ are used to determine the metal thickness and the dielectric thickness for all layers. For M1, we assume that the substrate and M2 are the ground planes; and for M4, we assume that M3 and M5 are the ground planes. The total capacitance, including the area capacitance, fringing capacitance, and coupling capacitance components, are obtained using the 3D field solver FastCap [2]. Based on these assumptions, our capacitance values for M1 closely match those given in the NTRS.

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Section: A Interconnect Modelingmentioning

confidence: 99%

Section: B Fmentioning

confidence: 99%

Section: A Interconnect Modelingmentioning

confidence: 99%

Section: A Interconnect Modelingmentioning

confidence: 99%

Section: A Wirelength Minimizationmentioning

confidence: 99%

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Interconnect design for deep submicron ICs

Cong

Pan

et al. 1997

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97

126

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A full-wave analysis of submicronic circuits in the microwave frequency range to estimate the input shape influence over VLSI interconnect performances

Servel

Huret

Paleczny

et al. 1999

Microw. Opt. Technol. Lett.

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Swarm Intelligence‐Inspired Spontaneous Fabrication of Optimal Interconnect at the Micro/Nanoscale

Huang

et al. 2016

Advanced Materials

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A spontaneous process is demonstrated to assemble nanoparticles into an optimal interconnect, as natural systems spontaneously figure out the shortest path. The optimal interconnect leads to a 65.9% decrease in electromagnetic interference, a 17.1% decrease in delay, and a 24.5% decrease in energy-delay. It will be of great significance for interconnect fabrication of versatile electronic circuits.

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Performance optimization of VLSI interconnect layout

Cited by 282 publications

References 47 publications

Interconnect design for deep submicron ICs

Interconnect design for deep submicron ICs

A full-wave analysis of submicronic circuits in the microwave frequency range to estimate the input shape influence over VLSI interconnect performances

Swarm Intelligence‐Inspired Spontaneous Fabrication of Optimal Interconnect at the Micro/Nanoscale

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