Performance Parameters of Low Power Sram Cells: A Review

Abstract

In this paper, various Low Power SRAM cell design techniques have been reviewed on the basis of power, stability, and delay. Many studies have proposed various SRAM architectures for different applications. It has been reported that 6T SRAM cell are high in speed but at low supply voltage, stability is a critical issue. It is found that 8T SRAM cell shows the highest level of stability at low supply voltage, but it has area penalty. Hence in this work all the required performance parameters of various SRAM cell architectures have been reviewed. This work will be helpful for VLSI designer to choose proper memory architecture as per applications. For example, machine learning needs high performance memory block while bio-medical implants require low power memory block. This paper also presents various tradeoffs between various design parameters of SRAM.Two ground-gated memory circuits are presented in this paper. Multi-threshold CMOS (MTCMOS) is a variation of CMOS chip technology which has transistors with multiple threshold voltages (V ) in order to optimize delay or power. th The asymmetrical 9T SRAM cell provides larger read current and shorter read delay. The Half-select technique is used in 9T SRAM cell for higher (Jiao et al., 2016a). Power ConsumptionJiao et al. (2016b) proposed a new asymmetrically groundgated seven-transistor SRAM cell. This new cell is introduced for providing a low leakage current and high data stability in sleep mode. The 65 nm CMOS technology is used for simulation. In their paper, the 7T SRAM cell was compared with the previously works on 6T and 8T SRAM cells. A special write circuitry is used for write operation in this 7T SRAM cell. The ground-gated technology is used to break the connection between power supplies to ground in idle mode, so that leakage current can reduce in sleep mode. A sleep transistor is connected between sources of access transistor to ground under the ground-gated technology. This sleep transistor works on high threshold value and ensures that there is no connection between power supply V to ground in sleep mode. For read operation, the output dd single-ended sense amplifier is connected at read port. In conventional 6T SRAM, the read and write operation performs on same bitline. So bitlines have to recharge at V dd after every write operation repeatedly. Therefore 7T SRAM cell does not need to be recharged to V after write dd operation because in this write, bitline is used only for write operation. Due to this difference, power consumption by memory array is higher in 6T SRAM cell compared to 7T SRAM cell. Leakage power can be reduced by using bit cell technique. This technique is affected by various parameters of SRAM cell (Shrivas and Akashe, 2012). The same port is shared for read and write operation in SRAM cell. If read and write will be separated, then leakage power consumption and stability can be improved. The 9T SRAM cell has different port for read and write operation, so this cell has better stability and low power dissipation (Akashe et al., ...

Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications

“…Tis cell, however, is adversely afected by the space and decrease the dynamic read power consumption. According to Nidhi et al [18], two access transistors and two straightforward cross-coupled inverters are often found in SRAM cells. Te access transistors that connect Bit Line (BL) are switched ON to enable operations.…”

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“…SRAM memory cell normally consists of simple cross-coupled inverters that are connected back to back, and two access transistors (Tiwari et al, 2017). Whenever a word line (WL) is activated for read or write operation, the access transistors are turned ON connecting the cell to the complementary bit line (BL) columns.…”