Performance trade-offs for microprocessor cache memories

Alpert, Donald; Flynn, Michael J.

doi:10.1109/40.7771

Cited by 30 publications

(4 citation statements)

References 9 publications

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“…Reducing cache block size while maintaining the same cache capacity requires implementing 8 × as much storage for cache block tags, which introduces signi cant area overhead. Instead, we extend cache blocks with just eight additional bits that each indicate whether a word in the cache block is valid or invalid, using sectored caches [74][75][76][77].…”

Section: Tracking Valid Wordsmentioning

confidence: 99%

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Sectored DRAM: An Energy-Efficient High-Throughput and Practical Fine-Grained DRAM Architecture

Olgun¹,

Bostanci²,

Oliveira³

et al. 2022

Preprint

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There are two major sources of ine ciency in computing systems that use modern DRAM devices as main memory. First, due to coarse-grained data transfers (size of a cache block, usually 64 B) between the DRAM and the memory controller, systems waste energy on transferring data that is not used in many workloads where a large fraction of words in a cache block is not used. Second, due to coarse-grained DRAM row activation, systems waste energy by activating DRAM cells that are unused in many workloads where spatial locality is lower than the large row size (usually 8-16 kB).We propose Sectored DRAM, a new, low-overhead DRAM substrate that alleviates the two ine ciencies, by enabling negrained DRAM access and activation. To e ciently retrieve only the useful data from DRAM, Sectored DRAM exploits the observation that many cache blocks are not fully utilized in many workloads due to poor spatial locality. Sectored DRAM predicts the words in a cache block that will likely be accessed during the cache block's cache residency and: (i) transfers only the predicted words on the memory channel, as opposed to transferring the entire cache block, by dynamically tailoring the DRAM data transfer size for the workload and (ii) activates a smaller set of cells that contain the predicted words, as opposed to activating the entire DRAM row, by carefully operating physically isolated portions of DRAM rows (MATs). Activating a smaller set of cells on each access relaxes DRAM power delivery constraints and allows the memory controller to schedule DRAM accesses faster. Thereby, Sectored DRAM improves memory latency and system performance for many workloads that frequently and irregularly access memory.Compared to prior work in ne-grained DRAM, Sectored DRAM greatly reduces DRAM energy consumption, does not reduce DRAM throughput, and can be implemented with low hardware cost. We evaluate Sectored DRAM using 41 workloads from widely-used benchmark suites. Compared to a system with coarse-grained DRAM, Sectored DRAM reduces the DRAM energy consumption of highly-memory-intensive workloads by up to (on average) 33% (20%) while improving their performance by up to (on average) 36% (17%). Sectored DRAM's DRAM energy savings, combined with its system performance improvement, allows system-wide energy savings of up to 23%.

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Section: Tracking Valid Wordsmentioning

confidence: 99%

“…Sectored caches [74][75][76][77] ( §5.2) require minor modi cations to existing cache design to enable word-granularity access. Our CACTI simulations show that these modi cations increase the L1 cache's access latency from 0.78 ns to 0.79 ns.…”

Section: Cache Access Latencymentioning

confidence: 99%

Sectored DRAM: An Energy-Efficient High-Throughput and Practical Fine-Grained DRAM Architecture

Olgun¹,

Bostanci²,

Oliveira³

et al. 2022

Preprint

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“…The problem is to find the best architecture that leads to a maximum of the main performance metrics: hit rate and utilization ratio. The utilization ratio can be defined as in [11]:…”

Section: Fault Tolerant Cache and Performance Metricsmentioning

confidence: 99%

Performance-Oriented Design of Fault Tolerant Cache Architectures

Novac¹,

Vari-Kakas²,

Novac³

et al. 2012

Proceedings of the 23rd International DAAAM Symposium 2012

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In this paper, we present aspects regarding the possibility of maximizing the performance/cost ratio in the cache memory design. A cache is a component that improves performance by transparently storing data so that future requests for that data can be served faster. Caches provide for efficient read/write access to memory, and their reliability is essential to assure dependable computing. Usually the cache design goal is to find such an architecture that maximizes the hit ratio. This paper offers the designer a computer simulation based method, taking into account classical performance metrics and reliability aspects.

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“…This work found that cache size and cycle time are dependent design parameters. Alpert and Flynn introduced an utilization model to evaluate the effect of the block size on cache performance [11]. They considered the actual physical area of caches and found that larger block sizes have better cost-performance ratio.…”

Section: R E La Te D W Orkmentioning

confidence: 99%