Persistency semantics of the Intel-x86 architecture

Abstract

Emerging non-volatile memory (NVM) technologies promise the durability of disks with the performance of RAM. To describe the persistency guarantees of NVM, several memory persistency models have been proposed in the literature. However, the persistency semantics of the ubiquitous x86 architecture remains unexplored to date. To close this gap, we develop the Px86 ('persistent x86') model, formalising the persistency semantics of Intel-x86 for the first time. We formulate Px86 both operationally and declaratively, and prove that the two characterisations are equivalent. To demonstrate the application of Px86, we develop two persistent libraries over Px86: a persistent transactional library, and a persistent variant of the MichaelśScott queue. Finally, we encode our declarative Px86 model in Alloy and use it to generate persistency litmus tests automatically.

PerSeVerE: persistency semantics for verification under ext4

“…3.3) does not require the p-ordering relation pb to be total and admits partial pb orders. This is in contrast to the existing literature on persistency [Raad et al 2018;2019a;b], which requires p-ordering to be a total order. Modelling pb as a partial order is highly effective in that it significantly reduces the number of executions to explore.…”

ARMv8-A System Semantics: Instruction Fetch in Relaxed Architectures

“…The closest is Raad et al's work on non-volatile memory, which models the required cache maintenance for persistent storage in ARMv8-A [39], as an extension to the ARMv8-A axiomatic model, and for Intel x86 [38] as an operational model, but neither are validated against hardware. In the sequential case, Myreen's JIT compiler verification [33] models x86 icache behaviour with an abstract cache that can be arbitrarily updated, cleared on a jmp.…”

Deciding reachability under persistent x86-TSO

“…This is why NVRAMs are often referred to as Persistent Memories (PMs). The combination of efficiency and persistency is a very attractive feature, breeding interest in PMs, and spurring research both in industry and academia [ARM 2018;Intel 2019b;Liu et al 2020;Raad et al 2020. Leading chip manufacturers such as Intel and ARM have started to integrate the technology in their chips [ARM 2018;Intel 2019b].…”

“…Developers are creating systems that directly manipulate PMs such as data bases [Arulraj and Pavlo 2017], key-value stores [Xia et al 2017], and custom programs [Cohen et al 2018]. [Raad et al 2020].…”

“…The manner in which data is persisted in the chip does not conform to TSO, and program runs, along which crashes occur, follow a weaker memory model than TSO. This is reflected in the operational model defined in [Raad et al 2020], called there Px86. Fig.…”