Perspective on Ferroelectric Devices: Lessons from Interfacial Chemistry

Abstract

Ferroelectric fluorite-structured oxide thin films have attracted increased interest from both academia and industry because of their superior scalability�in which their ferroelectric properties can be maintained even below 10 nm thickness�and excellent compatibility with current complementary metal−oxide− semiconductor technology. Regarding recent efforts to downscale the technology node of semiconductor processing, the emergence of ferroelectric properties in fluorite-structured oxide thin films at small length scales is of particular interest. As the length scale of the fluorite-structured oxide thin films reaches the atomic scale, the contribution of the interfacial layer to the properties naturally increases. In particular, the quality and type of interfacial layer, as well as the reaction chemistry in response to the electric field, play a major role in determining the properties of the devices. Consequently, understanding the chemistry of ferroelectric−electrode and ferroelectric−semiconductor interfaces is crucial for their use in industrial applications in the near future. In this context, emerging semiconductor devices based on fluorite-structured oxide ferroelectrics, including ferroelectric field-effect transistors, ferroelectric random-access memories, and ferroelectric tunnel junctions, and the impact of interface chemistry in the devices are reviewed in detail.

The Potential of ferroelectric HfO2 for Next-Generation Memory Device: Ferroelectric Properties and Applications

“…분극 방향에 따른 V T 와 MW를 이상적으로 나타내 면, 다음과 같다. [32] (식 1) 역할을 한다. [33,34] 한 개의 트랜지스터와 한 개의 축전기로 이루어진 극을 사용하더라도 불가피한 것이다.…”

“…[59][60][61] HfO 2 가 1 nm 두께에서도 강유전성을 유지할 수 있 다는 점은 FTJ소자 개선에 매우 유용하다. [65] Lee et 32,1904123., with permission of John Wiley & Sons, Ltd [67] . Copyright2023, with permission from Elsevier [66] .…”

Hafnia-Based Ferroelectric Memory: Device Physics Strongly Correlated with Materials Chemistry

“…The current challenge lies in the difficulty of turning on the channel of FeFET without affecting the V th state, as reported in the literature. Equations and show low (programmed, V th,ERS ) and high (erased, V th,PRG ) V th of FeFETs. , V th , ERS = V FB , 0 + max true( 4 q N normala k normals ε 0 ϕ normalB − P normalr C FE , prefix− V normalc true) V th , PRG = V FB , 0 + min true( 4 q N normala k normals ε 0 ϕ normalB + P normalr C FE , V normalc true) Here, V FB , ϕ B , q , N a , k s , ε 0 , C DE , and C FE denote the flat-band voltage, the difference between the intrinsic and extrinsic Fermi levels in bulk Si, the unit charge, the acceptor doping concentration, dielectric constant of Si, the vacuum permittivity, the capacitance of the gate dielectric, and the capacitance of ferroelectric layer, respectively. 2ϕ B denotes the...…”

“…It should be noted that further studies to suppress the nonferroelectric phase formation and to deposit ferro- Besides polymorphism, extrinsic factors can affect various material properties and device performances. 7,34,35 Despite the importance of the effect of extrinsic factors on device physics, perspectives on the ultimately expected device performance based on the well-established physics of ferroelectric materials have yet to be comprehensively presented. In this Perspective, our purpose is to provide a perspective on ferroelectric memory devices based on the physical chemistry in (Hf,Zr)O 2 ferroelectrics.…”

“…Equations 1 and 2 show low (programmed, V th,ERS ) and high (erased, V th,PRG ) V th of FeFETs. 35,93 V V…”