Phase-Based Application-Driven Hierarchical Power Management on the Single-chip Cloud Computer

Ioannou, Nikolas; Kauschke, Michael; Gries, Matthias; Cintra, Marcelo

doi:10.1109/pact.2011.19

Cited by 39 publications

(15 citation statements)

References 28 publications

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“…For measuring the node power and energy consumption, a Wattsup 6 power meter is used with a sampling rate of 1 Hz. The user defined target performance loss γ is taken as 10% which is a typical value to achieve energy savings (see, e.g., [10]. Due to a low measuring resolution of Wattsup and for consistency, a large number of executions were performed.…”

Section: Resultsmentioning

confidence: 99%

Runtime Procedure for Energy Savings in Applications with Point-to-Point Communications

Sundriyal

Sosonkina

Gaenko

2012

2012 IEEE 24th International Symposium on Computer Architecture and High Performance Computing

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Although high-performance computing has always been about efficient application execution, both energy and power consumption have become critical concerns owing to their effect on operating costs and failure rates of large-scale computing platforms. Modern microprocessors are equipped with the capabilities to reduce their power consumption using techniques such as dynamic voltage and frequency scaling (DVFS) and CPU clock modulation (called throttling). Without careful application, however, DVFS and throttling may cause a significant performance loss due to system overhead. This work presents design considerations for a runtime procedure that dynamically analyzes blocking point-to-point communications, groups them according to the proposed criteria, and applies frequency scaling by analyzing both communication and architectural parameters without penalizing the performance much. Experiments, performed on NAS parallel benchmarks verify the proposed design by exhibiting energy savings of as much as 11% with a performance loss as low as 2%.

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Section: Resultsmentioning

confidence: 99%

Runtime Procedure for Energy Savings in Applications with Point-to-Point Communications

Sundriyal

Sosonkina

Gaenko

2012

2012 IEEE 24th International Symposium on Computer Architecture and High Performance Computing

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“…The user-defined performance-loss tolerance γ is taken as 10%, which is a typical value to allow for energy savings (see, e.g. [25]). which is referred to as silatrane-265 in the rest of the paper.…”

Section: Experiments Setupmentioning

confidence: 99%

Core and Uncore Joint Frequency Scaling Strategy

Sundriyal¹,

Sosonkina²,

Westheimer³

et al. 2018

JCC

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Energy-proportional computing is one of the foremost constraints in the design of next generation exascale systems. These systems must have a very high FLOP-per-watt ratio to be sustainable, which requires tremendous improvements in power efficiency for modern computing systems. This paper focuses on the processor-as still the biggest contributor to the power usage-by considering both its core and uncore power subsystems. The uncore describes those processor functions that are not handled by the core, such as L3 cache and on-chip interconnect, and contributes significantly to the total system power. The uncore frequency scaling (UFS) capability has been available to the user since the Intel Haswell processor generation. In this paper, performance and power models are proposed to use both the UFS and dynamic voltage and frequency scaling (DVFS) to reduce the energy consumption in parallel applications. Then, these models are incorporated into a runtime strategy that performs processor frequency scaling during parallel application execution. The strategy can be implemented at the kernel/firmware level, which makes it suitable for improving the energy efficiency of exascale design. Experiments on a 20-core Haswell-EP machine using the quantum chemistry application GAMESS and NAS benchmark resulted in up to 24% energy savings with as little as 2% performance loss.

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“…Several [4]. The phase detector is designed by instrumenting MPI calls to measure the execution time of each call and the execution time of the program in between calls.…”

Section: Related Workmentioning

confidence: 99%

“…The majority of DVFS research assumes the power controlability of individual computing elements, for example, Cai et al [2], Gamell et al [1], Lim et al [3], Iannou et al [4,5], and Poellabauer et al [13]. This is also the case for Chen et al [10] with the focus on server farms.…”

Section: Uniform Vs Core-based Controlmentioning

confidence: 99%

Dynamic power management for reactive stream processing on the SCC tiled architecture

et al. 2016

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Dynamic voltage and frequency scaling (DVFS) is a means to adjust the computing capacity and power consumption of computing systems to the application demands. DVFS is generally useful to provide a compromise between computing demands and power consumption, especially in the areas of resource-constrained computing systems. Many modern processors support some form of DVFS. In this article, we focus on the development of an execution framework that provides lightweight DVFS support for reactive stream processing systems (RSPS). RSPs are a common form of embedded control systems, operating in direct response to inputs from their environment. At the execution framework, we focus on support for many-core scheduling for parallel execution of concurrent programs. We provide a DVFS strategy for RSPs that is simple and lightweight, to be used for dynamic adaptation of the power consumption at runtime. The simplicity of the DVFS strategy became possible by the sole focus on the application domain of RSPs. The presented DVFS strategy does not require specific assumptions about the message arrival rate or the underlying scheduling method. While DVFS is a very active field, in contrast to most existing research, our approach works also for platforms like many-core processors, where the power settings typically cannot be controlled individually for each computational unit. We also support dynamic scheduling with variable workload. While many research results are provided with simulators, in our approach, we present a parallel execution framework with experiments conducted on real hardware, using the single-chip cloud computer many-core processor. The results of our experimental evaluation confirm that our simple DVFS strategy provides potential for significant energy saving on RSPs.

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Phase-Based Application-Driven Hierarchical Power Management on the Single-chip Cloud Computer

Cited by 39 publications

References 28 publications

Runtime Procedure for Energy Savings in Applications with Point-to-Point Communications

Runtime Procedure for Energy Savings in Applications with Point-to-Point Communications

Core and Uncore Joint Frequency Scaling Strategy

Dynamic power management for reactive stream processing on the SCC tiled architecture

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