Phase-based Cache Locking for Embedded Systems

Adegbija, Tosiron; Gordon‐Ross, Ann

doi:10.1145/2742060.2742076

Cited by 9 publications

(2 citation statements)

References 17 publications

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“…2) LARS-Optimal: For easy practical implementation, we designed LARS-Optimal as a simple heuristic/algorithm to determine the best retention times during runtime. The algorithm determines the best retention time using a cache energy model [28] based on the number of cache accesses, writebacks, misses, and the associated latencies.…”

Section: B Lars Architecturementioning

confidence: 99%

Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design

Kuan

Adegbija

2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Much research has shown that applications have variable runtime cache requirements. In the context of the increasingly popular Spin-Transfer Torque RAM (STT-RAM) cache, the retention time, which defines how long the cache can retain a cache block in the absence of power, is one of the most important cache requirements that may vary for different applications. In this paper, we propose a Logically Adaptable Retention Time STT-RAM (LARS) cache that allows the retention time to be dynamically adapted to applications' runtime requirements. LARS cache comprises of multiple STT-RAM units with different retention times, with only one unit being used at a given time. LARS dynamically determines which STT-RAM unit to use during runtime, based on executing applications' needs. As an integral part of LARS, we also explore different algorithms to dynamically determine the best retention time based on different cache design tradeoffs. Our experiments show that by adapting the retention time to different applications' requirements, LARS cache can reduce the average cache energy by 25.31%, compared to prior work, with minimal overheads.

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Section: B Lars Architecturementioning

confidence: 99%

Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design

Kuan

Adegbija

2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Liu et al pointed out in [26] that it is NP difficult to reduce the average case executing time of the system through static cache locking. Adegbija and Gordon-Ross [18] present a phase-based locking technique for data caches. Their technique divides the execution into intervals and groups the intervals with similar characteristics into phases showing data reuse.…”

Section: A Static Cache Lockingmentioning

confidence: 99%

A Dynamic Instruction Cache Locking Approach for Minimizing Worst Case Execution Time of a Single Task

et al. 2020

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In real time embedded system, the embedded software often consists of a set of concurrent tasks, and such tasks are generally subject to timing constraints. In order to satisfy all the timing constraints, precisely predicting the WCET of a task is essential for the task scheduler to construct a feasible schedule for a task set. Caches have been widely used to bridge the gap between high speed processors and relatively slower off-chip memory. However, caches make it extremely harder to predict precise WCET (Worst Case Execution Time ) of a task for the simple reason that it is difficult to predict if each cache access is a cache hit or miss. Cache locking is a mechanism which disables the replacement policy of caches and locks some contents (instruction or data) in the caches, such that the accesses to those contents become fully predictable and the WCET of a task is easier to predict. Furthermore, cache locking is also an effective technique to reduce the WCET of a task by locking appropriate contents in the caches. In this paper, we investigate the WCET-aware I-cache (Instruction cache) locking problem and propose an ILP-based (Integer Linear Programming) dynamic I-cache locking approach for reducing the WCET of a task. Our approach not only select locking contents which have largest benefit for reducing WCET of a task, but also finds a good locking point for each locked instruction such that extra execution time spend on locking instructions is also minimized. We have implemented this approach and compared it with two state-of-theart I-cache locking approaches, the longest path based dynamic cache locking approach proposed in and the min-cut based dynamic locking approach proposed in by using MRTC benchmark suite. The experimental results show that our approach performs better for each benchmark. Compared to the longest path based dynamic approach, our approach achieves the average improvements of 5.8%, 13.8%, 16.1% and 12.6% for the 256B, 512B, 1KB and 2KB caches, respectively. Compared to the min-cut based dynamic approach, our approach achieves the average improvements of 2.2%, 7.6%, 8.2% and 6.4% for the 256B, 512B, 1KB and 2KB caches, respectively.INDEX TERMS Cache locking, real-time systems, worst-case-executing-time.

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