Phase-Change Technology and the Future of Main Memory

Lee, B.C.; Zhou, Ping; Yang, Jun; Zhang, Youtao; Zhao, Bo; Ïpek, Engin; Mutlu, Onur; Burger, Doug

doi:10.1109/mm.2010.24

Cited by 367 publications

(198 citation statements)

References 22 publications

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“…Recently, this traditional storage model is enriched by the new persistent memory technology -a new tier between traditional main memory and storage with attributes from both [6,30,47,54,59]. Persistent memory allows applications to perform loads and stores to manipulate persistent data, as if they are accessing traditional main memory.…”

Section: Introductionmentioning

confidence: 99%

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

Zhao

Mutlu²,

Xie

2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

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Abstract-Byte-addressable nonvolatile memories promise a new technology, persistent memory, which incorporates desirable attributes from both traditional main memory (byte-addressability and fast interface) and traditional storage (data persistence). To support data persistence, a persistent memory system requires sophisticated data duplication and ordering control for write requests. As a result, applications that manipulate persistent memory (persistent applications) have very different memory access characteristics than traditional (non-persistent) applications, as shown in this paper. Persistent applications introduce heavy write traffic to contiguous memory regions at a memory channel, which cannot concurrently service read and write requests, leading to memory bandwidth underutilization due to low bank-level parallelism, frequent write queue drains, and frequent bus turnarounds between reads and writes. These characteristics undermine the high-performance and fairness offered by conventional memory scheduling schemes designed for non-persistent applications.Our goal in this paper is to design a fair and high-performance memory control scheme for a persistent memory based system that runs both persistent and non-persistent applications. Our proposal, FIRM, consists of three key ideas. First, FIRM categorizes request sources as non-intensive, streaming, random and persistent, and forms batches of requests for each source. Second, FIRM strides persistent memory updates across multiple banks, thereby improving bank-level parallelism and hence memory bandwidth utilization of persistent memory accesses. Third, FIRM schedules read and write request batches from different sources in a manner that minimizes bus turnarounds and write queue drains. Our detailed evaluations show that, compared to five previous memory scheduler designs, FIRM provides significantly higher system performance and fairness.

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Section: Introductionmentioning

confidence: 99%

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

Zhao

Mutlu²,

Xie

2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

Self Cite

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“…Since these technologies have low idle power, high storage density, and good scalability properties compared to DRAM [1,2], they have been regarded as potential alternatives to replace or complement DRAM as the technology used to build main memory [3,4,5,6,7,8,9]. Perhaps even more importantly, the non-volatility property of these emerging technologies promises to enable memory-level storage (i.e., persistent memory), which can store data persistently at the main memory level at low latency [10,11,12,13,14,15,16].…”

Section: Introduction Emerging Non-volatile Memory (Nvm) Technologmentioning

confidence: 99%

“…Their DRAM-comparable performance and better-than-DRAM technology-scalability, which can enable high memory capacity at low cost, make these technologies promising alternatives to DRAM [3,4,5]. As such, many recent works examined the use of these technologies as part of main memory [3,4,5,6,7,8,9,10,11,12,13,14,15,16], providing disk-like data persistence at DRAM-like latencies.…”

Section: Introduction Emerging Non-volatile Memory (Nvm) Technologmentioning

confidence: 99%

Loose-Ordering Consistency for persistent memory

Shu

Sun

et al. 2014

2014 IEEE 32nd International Conference on Computer Design (ICCD)

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124

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Abstract-Emerging non-volatile memory (NVM) technologies enable data persistence at the main memory level at access speeds close to DRAM. In such persistent memories, memory writes need to be performed in strict order to satisfy storage consistency requirements and enable correct recovery from system crashes. Unfortunately, adhering to a strict order for writes to persistent memory significantly degrades system performance as it requires flushing dirty data blocks from CPU caches and waiting for their completion at the main memory in the order specified by the program. This paper introduces a new mechanism, called Loose-Ordering Consistency (LOC), that satisfies the ordering requirements of persistent memory writes at significantly lower performance degradation than stateof-the-art mechanisms. LOC consists of two key techniques. First, Eager Commit reduces the commit overhead for writes within a transaction by eliminating the need to perform a persistent commit record write at the end of a transaction. We do so by ensuring that we can determine the status of all committed transactions during recovery by storing necessary metadata information statically with blocks of data written to memory. Second, Speculative Persistence relaxes the ordering of writes between transactions by allowing writes to be speculatively written to persistent memory. A speculative write is made visible to software only after its associated transaction commits. To enable this, our mechanism requires the tracking of committed transaction ID and support for multi-versioning in the CPU cache. Our evaluations show that LOC reduces the average performance overhead of strict write ordering from 66.9% to 34.9% on a variety of workloads.

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“…As the increasing size of the memory system, the traditional DRAM-based main memory systems are starting to hit the cost and power limit [1,2,3]. In addition, flash memory has characteristics of not-in-place update, random write, and asymmetric I/O costs among read, write, and erase operations [4,5,6]. Hence, more effort should be taken to overcome the drawbacks to improve access performance of flash-based systems.…”

Section: Introductionmentioning

confidence: 99%

PCRAM-aware cluster allocation algorithm for hybrid main memory hierarchy

Chen

Zhou

et al. 2015

IEICE Electron. Express

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Phase Change Random Access Memory (PCRAM) has several characteristics that make it a promising candidate for main memory. In this paper, the challenges involved in incorporating PCRAM into the main memory hierarchy of flash-based systems are explored, and a hybrid memory hierarchy consisting of PCRAM and DRAM for SSD is proposed. To reduce the write traffic of Flash, a buffer management scheme for the hybrid memory is implemented. The proposed scheme above is implemented on basis of Disksim platform. The simulation results indicate that the proposed buffer algorithm can decrease the number of random write and erase operations of the SSD and improve the average system response rate obviously.

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Phase-Change Technology and the Future of Main Memory

Cited by 367 publications

References 22 publications

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

Loose-Ordering Consistency for persistent memory

PCRAM-aware cluster allocation algorithm for hybrid main memory hierarchy

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