Phase Interpolator-Based Clock and Data Recovery With Jitter Optimization

Souliotis, George; Tsimpos, Andreas; Vlassis, S.

doi:10.1109/ojcas.2023.3295649

Cited by 3 publications

(5 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The DNL is most significant form of linearity measurement of a phase interpolator because in a system, the designer mostly cares about the phase step error of the clocks produced by the phase interpolator. The DNL of this work is comparable to that of [6], [9], and [7] whereas the DNL of the other two digital phase interpolators, [3] and [2], are noticeably lower than the phase interpolator presented in this thesis.…”

Section: Performance Summary and Comparisonmentioning

confidence: 69%

“…From table 5.7, the power consumption advantage for digital phase interpolators is clear as [6] and [8] show significantly greater power consumption than the digital works. The interpolator presented in [7] is a CML implementation and shows the least power consumption, however this interpolator was designed in 28nm technology and using a 0.9V supply whereas this work was completed in 65nm technology and using 1.2V. The CML phase interpolator presented in [9] has only a slightly greater power consumption than this work and operates at the same frequency.…”

Section: Performance Summary and Comparisonmentioning

confidence: 97%

“…These phases are produced by some phase generator circuit which uses some reference clock that is of equal frequency to the received data. This phase generator can be PLL based or delay line based among other options [7]. For this example, the phase generator is shown in to produce 8 clock signals with phase steps of 45 degrees.…”

Section: Motivationmentioning

confidence: 99%

“…Therefore, some phase interpolator publications do not list INL in their performance summary. The CML phase interpolators in [7] and [9] have listed their INL as 0.27LSB and 2.5LSB, respectively. The INL of the interpolator of this thesis is 0.31, which is comparable to [7].…”

Section: Performance Summary and Comparisonmentioning

confidence: 99%

“…The CML phase interpolators in [7] and [9] have listed their INL as 0.27LSB and 2.5LSB, respectively. The INL of the interpolator of this thesis is 0.31, which is comparable to [7].…”

Section: Performance Summary and Comparisonmentioning

confidence: 99%

See 4 more Smart Citations

All Digital CMOS 5-BIT Phase Interpolator at 10 Gigahertz in 65NM Technology

Kooner

View full text Add to dashboard Cite

Phase interpolators are critical blocks in some clock and data recovery (CDR) systems.These interpolators are generally implemented using current-mode logic (CML). This work presents the design of an all-digital phase interpolator based on static CMOS logic gates and cells with a 5-bit resolution. This phase interpolator demonstrates functionality with input clock frequencies of 10 GHz while maintaining relatively low power consumption and acceptable linearity. The interpolator as a standalone block was characterized through post-layout simulations using extracted parasitics and simulating across process, voltage, and temperature (PVT) variations. This design achieves a worstcase power consumption of 6.7mW, DNL of 0.26 LSB, INL of 0.31 LSB, and a settling time of 4 clock cycles. This phase interpolator was partially fabricated as a component of a system. The system was fabricated in the TSMC 65nm general-purpose technology and process.

show abstract

Section: Performance Summary and Comparisonmentioning

confidence: 69%

Section: Performance Summary and Comparisonmentioning

confidence: 97%

Section: Motivationmentioning

confidence: 99%

Section: Performance Summary and Comparisonmentioning

confidence: 99%

“…The CML phase interpolators in [7] and [9] have listed their INL as 0.27LSB and 2.5LSB, respectively. The INL of the interpolator of this thesis is 0.31, which is comparable to [7].…”

Section: Performance Summary and Comparisonmentioning

confidence: 99%

See 3 more Smart Citations