Phase Locked Loop (PLL) based Clock and Data Recovery Circuits (CDR) using Calibrated Delay Flip Flop

Abstract

A Delay Flip Flop (DFF) is used in the phase detector circuit of the clock and data recovery circuit. A DFF consists of the three important timing parameters: setup time, hold time, and clock-to-output delay. These timing parameters play a vital role in designing a system at the transistor level. This thesis paper explains the impact of metastablity on the clock and data recovery (CDR) system and the importance of calibrating the DFF using a metastable circuit to improve a system's lock time and peakto-peak jitter performance. The DFF was modeled in MATLAB Simulink software and calibrated by adjusting timing parameters. The CDR system was simulated in Simulink for three different cases: 1) equal setup and hold times, 2) setup time greater than the hold time, and 3) hold time greater than the setup time. The Simulink results were then compared with the Cadence simulation results, and it was observed that the calibration of DFF using a metastable circuit improved the CDR system's lock time and jitter tolerance performance. The overall power dissipation of the designed CDR system was 2.4 mW from a 1 volt supply voltage. ACKNOWLEDGEMENTS I would like to express my gratitude to my advisor Dr. Shahab Ardalan for guiding me throughout this research with his invaluable knowledge. He was always supportive of my work since I began studying analog mixed signal courses at San Jose State University. I would also like to thank him for providing access to analog mixed signal (AMS) lab with the most recent simulation software tools that are used in the industry. Without his guidance, this research would have been incomplete. I also would like to thank my committee members Dr. Sotoudeh Hamedi-Hagh and Dr. M. J. Zoroofchi for serving as my committee members. I thank them for their immense support and their helpful ideas throughout my education and research at San Jose State University. A special thanks to my family. Words cannot express how grateful I am to my parents and siblings for always been supportive to my work, studies, and research. I am quite grateful to have all of you in my life. Without their encouragement, I would not have achieved this level of success thus far. v TABLES OF CONTENTS Chapter 1. Introduction .