Phase-Locking in High-Performance Systems

Razavi, Behzad

doi:10.1109/9780470545492

Cited by 105 publications

(57 citation statements)

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“…Because of their simple loop design, DLLs have been widely employed in applications where precise and robust phase alignment of the clock and data signals are required [30]. A common example of such applications is clock and data recovery (CDR) systems for high speed digital data streaming, where the phase of the buffered clock is locked to that of the input data [31]- [33].…”

Section: Introductionmentioning

confidence: 99%

“…Another example is the generation of accurate timing signals for the row and column strobes of dynamic random access memories (DRAM) [34]. However, since a DLL only contain a variable of phase but not that of a frequency, its applications have been historically limited compared to a PLL [30]. One of such applications for which a PLL is widely utilized, is the frequency synthesis for wireless applications with stringent requirements on the quality of the synthesized carrier signal.…”

Section: Introductionmentioning

confidence: 99%

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Analysis and Design of DLL-Based Frequency Synthesizers for Ultra-Wideband Communication

Ojani¹

2015

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Sweden Cover image:The cover image illustrates a sine-shaped "wordle" of the thesis.Printed by LiU-Tryck, Linköping University Linköping, Sweden, 2014 iii AbstractEver increasing demand for high speed transmission of large data between the electronic devices within a wireless personal area network has been motivating the development of the appropriate wireless standards. Ultra-wideband (UWB) communication employs the unlicensed frequency spectrum of 3.1 -10.6 GHz and utilizes a low average transmit power to offer the potential for high data rates in short range wireless links. WiMedia specification for UWB employs a frequency hopping scheme which requires a very fast hopping speed of 9.47 ns. Also, the strong interferers from the coexisting wireless technologies put stringent requirements on synthesizer's sideband spurs. Satisfying such challenging requirements using conventional frequency synthesis approaches is impractical and demands for exploration, analysis and design of new synthesizer architectures.Essential characteristics of a delay-locked loop (DLL), such as its first-order loop stability, relatively wide loop bandwidth, and low jitter accumulation, make DLL-based architectures attractive candidates for fast switching and low phase noise frequency synthesis applications. However, as an edge-combiner (EC) is required to produce different frequencies than that of the reference clock, any misalignment in equallyspaced DLL output edges will generate an erroneous periodicity, resulting in reference sideband spurs at the output spectrum of the frequency synthesizer.This thesis investigates the opportunities and challenges of employing DLL-based architectures to synthesize carrier frequencies for wireless applications, specifically UWB communication. The dissertation has contributed to two aspects of the topic; mathematical modeling and analysis, as well as circuit design and implementation.A comprehensive behavioral model of the harmonic spur levels in edge-combining DLL-based frequency synthesizers is developed which includes the effects of the stagedelay mismatch, the static phase error of the locked-loop, and the duty cycle distortion iv of the reference clock. Utilizing Fourier series representation of the DLL output phases, an analytical expression for synthesizer's spur levels is derived. Applying Taylor series approximations and moment methods to the analytical formula, closed-form expressions are obtained for the probability density function and mean value of the harmonic spur magnitudes. Finally, a Monte Carlo-free spur-aware design flow is introduced which significantly accelerates the iterative design procedure of the synthesizer. Accuracy and robustness of the prediction method against wide-range values of the non-idealities are investigated and verified through Monte Carlo simulations of the synthesizer's behavioral and transistor-level model in a 65-nm CMOS process.Three DLL-based architectures are developed and designed. In the first architecture, fast hopping frequency synthesis is achieve...

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Analysis and Design of DLL-Based Frequency Synthesizers for Ultra-Wideband Communication

Ojani¹

2015

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“…The electronic realizations of generators, multipliers, and filters can be found in (Wolaver, 1991;Best, 2003;Chen, 2003;Giannini & Leuzzi, 2004;Goldman, 2007;Razavi, 2001;Aleksenko, 2004). In the simplest case it is assumed that the filter removes from the input the upper sideband with frequency ω 1 (t)+ω 2 (t) but leaves the lower sideband ω 1 (t) − ω 2 (t) without change.…”

Section: Fig 1 Block Diagram Of Pll On the Level Of Electronic Realmentioning

confidence: 99%

“…In radio engineering PLL is applied to a carrier synchronization, carrier recovery, demodulation, and frequency synthesis (see, e.g., (Stephens, 2002;Ugrumov, 2000)). After the appearance of an architecture with chips, operating on different frequencies, the phase-locked loops are used to generate internal frequencies of chips and synchronization of operation of different devices and data buses (Young et al, 1992;Egan, 2000;Kroupa, 2003;Razavi, 2003;Shu & Sanchez-Sinencio, 2005;Manassewitsch, 2005). For example, the modern computer motherboards contain different devices and data buses operating on different frequencies, which are often in the need for synchronization (Wainner & Richmond, 2003;Buchanan & Wilson, 2001).…”

Section: Introductionmentioning

confidence: 99%

Nonlinear Analysis and Design of Phase-Locked Loops

Леонов¹,

Kuznetsov²,

Seledzhi³

2009

Automation Control - Theory and Practice

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“…Sufficient isolation must be achieved to avoid signal leakage, especially at higher VCO output frequencies [16].…”

Section: Band Selectorsmentioning

confidence: 99%

Very Wide Range Frequency Synthesizer Architecture for Avionic SDR Applications

Ismaili

Ajib

Gagnon

et al. 2015

2015 IEEE International Conference on Ubiquitous Wireless Broadband (ICUWB)

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Abstract-This paper presents a very wide range frequency synthesizer architecture appropriate to avionic software defined radio (SDR) applications. The synthesizer generates a continuous carrier frequencies range between 187 MHz and 12 GHz that covers most of avionic communication applications. The covered range is distributed into twenty sub-bands by using a voltage controlled oscillator (VCO). The considered VCO is able to achieve a tuning range from 10 GHz to 12 GHz (18.2%) and from 7 GHz to 8.5 GHz (19.35%). It includes a capacitor bank, varactors, and switched inductors and is designed in 0.13 µm CMOS technology. Using the advanced design system (ADS) simulation tool and SpectreRF simulator, the proposed VCO exhibits a phase noise of -125 dBc/Hz at 12 GHz and at a 10 MHz offset frequency with a power consumption of 4.1 mW. At 10 GHz, the simulated synthesizer phase noise is of -102 dBc/Hz at a 1 MHz frequency offset. In addition, the loop bandwidth of the phase locked loop (PLL) is 1.1 MHz whereas the settling time is 3.64 µs.

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Phase-Locking in High-Performance Systems

Cited by 105 publications

References 0 publications

Analysis and Design of DLL-Based Frequency Synthesizers for Ultra-Wideband Communication

Analysis and Design of DLL-Based Frequency Synthesizers for Ultra-Wideband Communication

Nonlinear Analysis and Design of Phase-Locked Loops

Very Wide Range Frequency Synthesizer Architecture for Avionic SDR Applications

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