Phase noise and jitter modeling for fractional-N PLLs

We present an integrated fractional-N lownoise frequency synthesizer for satellite applications. By using two integrated VCOs and combining digital and analog tuning techniques, a PLL lock range from 8 to 12 GHz is achieved. Due to a small VCO fine tuning gain and optimized charge pump output biasing, the phase noise is low and almost constant over the tuning range. All 16 sub-bands show a tuning range above 900 MHz each, allowing temperature compensation without sub-band switching. This makes the synthesizer robust against variations of the device parameters with process, supply voltage, temperature and aging. The measured phase noise is -87 dBc/Hz and -106 dBc/Hz at 10 kHz and 1 MHz offset, respectively. In integer-N mode, phase noise values down to -98 dBc/Hz at 10 kHz and -111 dBc/Hz at 1 MHz offset, respectively, were measured.

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“…We use the analytical linear fourth-order PLL model presented in [29] to optimize the loop filter. For the voltage divider we assume R5 = R4.…”

Section: Modeling Resultsmentioning

confidence: 99%

An integrated 8-12 GHz fractional-N frequency synthesizer in SiGe BiCMOS for satellite communications

Peters

Osmany

et al. 2010

Analog Integr Circ Sig Process

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“…First, the noise contributed from each block should be found. Each block could contribute voltage noise, current noise, or phase noise according to the nature and the behavior of this block [37], [38], [39], [40], [41], [42]. Table 3.…”

Section: Effects a Phase Noise (Timing Jitter)mentioning

confidence: 99%

Increasing the Modeling Accuracy of an Analog PLL Device Executed With an Event-Driven Simulator

Maurice,

Dessouky,

Salem

2023

IEEE Access

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Real Number Modelling (RNM) has become more common as a part of mixed-signal SoC validation. The paper illustrates modelling Phase Locked Loops (PLL) using SystemVerilog-Real Number Modelling (SV-RNM) as it's one of the essential blocks in any Integrated Circuit (IC) and a feedback loop system. It uses the Piece-Wise Linear (PWL) technique to model the loop filter with higher orders, higher than a first-order Low Pass Filter (LPF). The PWL technique needs both the value and the slope information so that the values between the samples can be interpolated, this is represented by the User-Defined Type (UDT) and Net (UDN). A fractional divider is modelled using the Sigma-Delta modulator of the Multi-stAge noiSe sHaping (MASH) 1-1-1 topology to generate the fractional part. Modelling non-linear effect like the phase noise of each sub-block, which is converted to the Root Mean Square (RMS)-jitter, by using the 'class' datatype that takes complex variables of real and imaginary values then returns some functionalities on these complex variables. Moreover, taking the loading effect due to capacitances and resistances at the output by using the User-Defined Resolved Nets (UDRN). The simulation results ensure that there is an accuracy improvement in the expected PLL outputs compared to the outputs from the transistor level with a much faster simulation time as an event-driven simulator is used.INDEX TERMS Real number modeling (RNM), SystemVerilog (SV), user-defined types (UDT), userdefined resolved nets (UDRN), phase locked loops (PLL), fractional dividers, piece-wise linear (PWL), phase noise (PN), RMS jitter, hardware description and verification language (HDVL).

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“…This is because frequency synthesis is taken into account, and the synthesizer’s voltage controlled oscillator (VCO) dominates at higher frequencies. More information on phase noise in frequency synthesizers is available in [ 16 , 17 ]. While a rubidium clock remains stable (i.e., does not drift) over longer periods of time relative to a crystal oscillator, it does not necessarily have lower phase-noise.…”

Section: Receiver Clock Comparisonmentioning

confidence: 99%

A GPS Phase-Locked Loop Performance Metric Based on the Phase Discriminator Output

Stevanović

Pervan

2018

Sensors

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We propose a novel GPS phase-lock loop (PLL) performance metric based on the standard deviation of tracking error (defined as the discriminator’s estimate of the true phase error), and explain its advantages over the popular phase jitter metric using theory, numerical simulation, and experimental results. We derive an augmented GPS phase-lock loop (PLL) linear model, which includes the effect of coherent averaging, to be used in conjunction with this proposed metric. The augmented linear model allows more accurate calculation of tracking error standard deviation in the presence of additive white Gaussian noise (AWGN) as compared to traditional linear models. The standard deviation of tracking error, with a threshold corresponding to half of the arctangent discriminator pull-in region, is shown to be a more reliable/robust measure of PLL performance under interference conditions than the phase jitter metric. In addition, the augmented linear model is shown to be valid up until this threshold, which facilitates efficient performance prediction, so that time-consuming direct simulations and costly experimental testing can be reserved for PLL designs that are much more likely to be successful. The effect of varying receiver reference oscillator quality on the tracking error metric is also considered.

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Phase noise and jitter modeling for fractional-N PLLs

Cited by 17 publications

References 13 publications

An integrated 8-12 GHz fractional-N frequency synthesizer in SiGe BiCMOS for satellite communications

An integrated 8-12 GHz fractional-N frequency synthesizer in SiGe BiCMOS for satellite communications

Increasing the Modeling Accuracy of an Analog PLL Device Executed With an Event-Driven Simulator

A GPS Phase-Locked Loop Performance Metric Based on the Phase Discriminator Output

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