Photoluminescence characterization of strained Si-SiGe-on-insulator wafers with different Ge fractions

Wang, Dong; Nakashima, Hiroshi; Matsumoto, Koji; Nakamae, M.

doi:10.1063/1.2152109

Cited by 22 publications

(11 citation statements)

References 16 publications

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“…It can be seen that samples with Ge%=15% showed better qualities than those with Ge%=20%. This is reasonable because high Ge fraction degrades quality of St-Si/SGOI wafer [5,6]. The T ox also showed effect on the wafer quality.…”

Section: Pl Evaluation For St-si/sgoi Wafersmentioning

confidence: 95%

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Development of strained Si-SiGe-on-insulator wafers for high speed ULSI

Nakashima

Miyao

Nakamae

et al. 2006

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings

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Strain relaxation process of SiGe-on-insulator (SGOI) structures in the oxidation induced Ge condensation method was investigated as a function of SiGe thickness. Complete relaxation was obtained for SiGe layer having the thickness of more than 60 nm, leading to the establishment of highly relaxed SGOI wafer fabrication. The photoluminescence evaluation of the strained Si/SGOI wafers showed high Ge fraction degrades crystallinity of St-Si/SGOI wafer, and high Ge condensation temperature is beneficial to the crystallinity enhancement. CMOS inverters and ring oscillators were fabricated to evaluate the impact of Strained-Si/SGOI on the device performance. The signal propagation speed of the CMOS on the St-Si/SGOI wafer was twice as high as that of the Si-on-insulator CMOS. IntroductionStrained Si (St-Si) technology benefits the carrier mobility, enables a way to fabricate low-power-consumption and high-speed devices. In general, St-Si epitaxially grows on a virtual substrate of SiGe alloy, which induces the strain and dominates the quality of the St-Si. Besides the strain induction, a virtual substrate of SiGe on insulator (SGOI) brings additional advantages of a Si-on-insulator (SOI) structure, which is superior to the bulk type SiGe. However, the fabrication of high-quality SGOI is relatively difficult because of the complicated wafer structure, in which many important parameters should be concerned, such as SiGe crystallinity and lattice relaxation of SiGe layer.To fabricate high quality SGOI, Tezuka et al. proposed a method of the Ge condensation by dry oxidation of the SiGe on SOI substrate [1]. By using this method, high lattice-relaxation-ratio (LRR) and thin SGOI with relatively low dislocation density can be achieved [1][2][3][4]. However, influences of SGOI thickness on the strain-relaxation process have not been clarified yet. To fabricate qualified St-Si/SGOI wafer, it is necessary to optimize the Ge condensation method. Based on the achievement of good-quality SGOI virtual substrate, St-Si can be epitaxially grown on the SGOI.Consequently, the quality evaluation should be done for the St-Si/SGOI wafer to qualify the wafer for device fabrication. After that, the advantage of St-Si/SGOI

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Section: Pl Evaluation For St-si/sgoi Wafersmentioning

confidence: 95%

“…PL measurements were performed with the same facilities as those used in Ref. [5,6]. Figure 4 shows the PL signals from all the samples.…”

Section: Pl Evaluation For St-si/sgoi Wafersmentioning

confidence: 99%

Development of strained Si-SiGe-on-insulator wafers for high speed ULSI

Nakashima

Miyao

Nakamae

et al. 2006

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings

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“…Since the diffusion length of free exciton (FE) is a few ms in the top layers (TL) above the BOX [3], PL represents the average quality of the TL. On the other hand, since the BOX layer terminates FE diffusion, PL should only 1-4244-0161-5/06/$20.00 ©2006 IEEE receive contributions from the TL [4]. PL measurements were performed with the same facilities as those used in Ref.…”

Section: Methodsmentioning

confidence: 99%

Photoluminescence Evaluation of Defects Generated during Temperature Ramp-up Process of SiGe-On-Insulator Virtual Substrate Fabrication

Wang

Ikeda

Nakashima

2006

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings

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Defects generated during the temperature ramping process were evaluated by photoluminescence (PL) for Si/SiGe/Si-on-insulater structure, which is the typical structure for SiGe-on-insulator (SGOI) virtual substrate fabrication using the Ge condensation by dry oxidation. The free exciton peaks were clearly observed for the as grown wafers and decreased with the increase of annealing temperature. Defect-related PL signals at around 0.82, 0.88, 0.95 and 1.0 eV were observed and they also varied according to the annealing temperature and SiGe thickness. The defect-related PL signals were also correlated to dislocation-related defects by transmission electron microscopy (TEM).

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“…Optical spectroscopy tests are convenient to probe the electronic structure of bulk insulators [12] as well as thin semiconductor material layers [13]. Moutanabbir et al [14] and Munguia et al [15] reported mechanical stress measurements in thin strained Silicon-OnInsulator (sSOI) layers using Raman and photoluminescence spectroscopy.…”

Section: Confocal Microscopy Measurementsmentioning

confidence: 98%