Physical Compact Model for Three‐Terminal SONOS Synaptic Circuit Element

Abstract

Improvements in computing performance and efficiency recently opened up opportunities [1] in artificial intelligence (AI), represented by the seminal work of Alex Krizhevsky et al. [2] in 2012 where graphic processing units (GPUs) combined with big data excelled on an image classification task (top-5 error rate of 15.3% achieved by artificial neural networks vs 26.2% from the runner-up algorithms). This achievement reignited the attention for deep neural networks dating back to the 1980s, [3,4] in particular for convolutional neural networks (CNNs). Further efforts to optimize computing hardware are being actively pursued, such as using fieldprogrammable gate arrays (FPGAs) and application-specific integrated circuits (ASICs), [5,6] including the tensor processing units (TPUs) [7,8] developed by Google and system on a chip (SoC)-scale AI accelerators used in mobile phones. This recent progress in computing hardware is still bound to CMOS technology, where the von Neumann bottleneck [9] limits speed and power efficiency. In-memory analog computing based on Ohm's and Kirchhoff 's laws, [10][11][12] utilizing nonvolatile memories (NVMs), such as resistive random access memory (RRAM), [13][14][15] phase-change memory (PCM), [16,17] and flash memory, [18][19][20][21] is a promising route to eliminate the von Neumann bottleneck and implement neuromorphic computing circuits for future AI systems. [22][23][24][25][26] Here we present a dynamical compact model for three-terminal silicon-oxide-nitride-oxide-silicon (SONOS) synaptic circuit elements. Three-terminal memory devices such as floating gate (FG) or SONOS flash memories have a long history for manufacturable data storage applications, but their compact models have relied on static metal-oxide-semiconductor field-effect transistor (MOSFET) behavior. [27][28][29] Moreover, a significant number of three-terminal synaptic devices are now being reported with various material systems, [30][31][32] but most publications describe experimental characterization without supplying a compact model, [33] so there exists a significant gap between the device community and circuit designers. Our work addresses this gap by constructing a well-posed compact model for three-terminal synaptic circuit elements, [34][35][36] beginning with the technologically mature SONOS device, which is a staple for NAND flash memory products. [37][38][39][40] In this work, we utilized technology computeraided design (TCAD) physics-based calculations within Synopsys Sentaurus to simulate the physics of a device and identified a key state variable Q M , the amount of charge in the SONOS trap layer, to guide us in constructing a compact model. Subsequently, we validated the model through a circuit simulation using Cadence Spectre to compare with the experimentally measured behavior of source-drain current after applying a wide range of voltage pulse amplitudes on the gate of a SONOS device. The use of both physics-based simulations and experimental data to identify the state variables and calibrate the ...

Abisko: Deep codesign of an architecture for spiking neural networks using novel neuromorphic materials

“…Nevertheless, developing and experimentally validating a compact model for SONOS represents a valuable knowledge-generating activity for modeling other three-terminal analog nonvolatile memories such as ECRAM. To this end, we have recently developed a well-poised physics-based compact model for a SONOS analog synaptic element in collaboration with Yi et al (2022). The model contains a nonvolatile memristor with the state variable Q M to represent the memristor charge under the gate of the three-terminal element.…”