2008 14th IEEE International on-Line Testing Symposium 2008
DOI: 10.1109/iolts.2008.23
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Physical Demonstration of Polymorphic Self-Checking Circuits

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Cited by 35 publications
(14 citation statements)
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“…Mutual collaboration between research teams at Brno University of Technology (The Microelectronics Department at The Faculty of Electrical Engineering and Communication represented by Mr. Roman Prokop and The Faculty of Information Technology) has enabled the creation of polymorphic gate with two inputs, whose function is controlled by supply voltage [11]. The fundamental goal of this joint effort was to come up with a gate design which is compatible with wide-spread CMOS based circuits (one of the essential requirements that should facilitate its use together with conventional CMOS gates on a single chip).…”
Section: Used Nand/nor Polymorphic Gatementioning
confidence: 99%
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“…Mutual collaboration between research teams at Brno University of Technology (The Microelectronics Department at The Faculty of Electrical Engineering and Communication represented by Mr. Roman Prokop and The Faculty of Information Technology) has enabled the creation of polymorphic gate with two inputs, whose function is controlled by supply voltage [11]. The fundamental goal of this joint effort was to come up with a gate design which is compatible with wide-spread CMOS based circuits (one of the essential requirements that should facilitate its use together with conventional CMOS gates on a single chip).…”
Section: Used Nand/nor Polymorphic Gatementioning
confidence: 99%
“…AND/OR 27/125°C Temperature 6 [14] AND/OR/XOR 3.3/0.0/1.5V External signal 10 [14] AND/OR 3.3/0.0V External signal 6 [4] NAND/NOR/XOR/AND 0.0/0.9/1.1/1.8V External signal 11 [18] AND/OR 1.2/3.3V V dd 8 [19] NAND/NOR 3.3/1.8V V dd 6 (fabricated) [20] NAND/NOR 5/3.3V V dd and/or temperature 8 (fabricated) [11] NAND/XOR 0/5V External Signal 9 [19] It is possible to recognize that the gate is composed of eight MOS transistors (3 n-MOS a 5 p-MOS). For the purpose of comparison let's take into account the following: common NAND or NOR gate built with CMOS technology contains exactly four transistors.…”
Section: Conditions Of Function Change No Of Transistors Published Inmentioning
confidence: 99%
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“…Figure 4 shows the behavior of the gate for two different levels of Vdd. Its detailed description and characterization is given in [17]. As the gate is crucial for the REPOMO32 behavior, we will briefly describe its implementation and properties.…”
Section: Repomo32 Descriptionmentioning
confidence: 99%
“…Another NAND/NOR gate controlled by Vdd was developed and characterized by FIT (Faculty of Information Technology) Evolvable Hardware Group [17]. The FIT gate was fabricated using AMIS CMOS 0.7 micron technology.…”
Section: Introductionmentioning
confidence: 99%