Physical Failure Analysis Deprocessing and Cross-Section Techniques for Cu/Low-k Technology

Wu, Huixian; Hooghan, Kultaransingh; Cargo, J.

doi:10.1109/tdmr.2004.824358

Cited by 4 publications

(1 citation statement)

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“…It is known that RC delay (R is the resistance and C is the coupled capacitance) and crosstalk are determined by parasitic elements corresponding to the connection lines. Copper (Cu) has been reported as one of promising materials for VLSI and SoC interconnects in nanodevice era [1][2][3][4][5][6][7][8]. However, due to the behavior of electron migration, Cu interconnects may differ from the original design pattern.…”

Section: Introductionmentioning

confidence: 99%

Three-dimensional simulation of nanoscale copper interconnects

Chou

Li²

5th IEEE Conference on Nanotechnology, 2005.

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Copper (Cu) interconnects are one of promising approaches for design and fabrication of gigascale ultra-large scale integrated (ULSI) circuit. In this paper, three configurations of interconnect, the parallel lines, the parallel lines on a plane, and the parallel lines between two planes are investigated. Three-dimensional simulation is performed by solving an electrostatic model using adaptive computing technique. For the studied three configurations, delay of resistance and capacitance (RC) is calculated with respect to different line spacing, line distance to plane, line width, and line height. Equivalent circuit is implemented for circuit simulation, and calculation of timing delay and crosstalk. It is found that RC time constant not only depends on the configurations but also dominates by the ratio of line height to line width. For sub-100 nm fabrication technology, there is an optimal design with respect to the three configurations. If the ratio of line height to line width is larger than 1, the RC time constant reaches to a minimum.

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