Physical modeling of hot-carrier degradation in nLDMOS transistors

Abstract

Our physics-based HCD model has been validated using scaled CMOS transistors in our previous work. In this work we apply this model for the first time to a high-voltage nLDMOS device. For the calculation of the degrading behaviour the Boltzmann transport equation solver ViennaSHE is used which also requires high quality adaptive meshing. We discuss the influence of the different model components in the different device regions. Finally we compare the model to experimental degradation results and show that each one gives a significant contribution to the result and that all of them are needed in order to satisfactorily fit the experimental data. I. INTRODUCTIONThe LDMOS transistor is one of the most popular devices employed in mixed-signal integrated circuits and in highvoltage automotive applications [1]. Hot-carrier degradation (HCD) still remains one of the main reliability concerns in these devices [1], [2], [3], [4]. This makes a predictive physical model for HCD in LDMOS very attractive. At the same time, such a model is extremely challenging to develop because of the complexity of the HCD-phenomenon and the complicated topological structure of the LDMOS.In fact, the physical origin of HCD is related to the generation of traps at or near the Si/SiO 2 interface. This generation is due to hot and cold carriers triggering singlecarrier and multiple-carrier dissociation mechanisms [5], [6], [7]. Thus, the key information needed for proper HCD modeling is the carrier energy distribution functions (DFs), which determine the rates of both aforementioned processes. This information can be obtained from a solution of the Boltzmann transport equation (BTE) [5]. Such a solution is challenging even for planar CMOS devices with a simpler architecture and becomes extremely demanding for such devices as the LDMOS transistor. This device has a non-planar interface with a non-trivial distribution of the electric field near the bird's beak (see Figs. 1,3), where the impact ionization spot, and hence the hot-carrier degradation spot are located [3], [4].In this work we apply our physics-based HCD modelwhich has been validated using scaled CMOS transistors with a gate length as short as 65 nm [6], [7] -to represent the linear drain current change due to HCD in a high-voltage device, i.e. the nLDMOS, for the first time.

Modeling of Hot-Carrier Degradation in nLDMOS Devices: Different Approaches to the Solution of the Boltzmann Transport Equation

“…1), and also high doping gradients in different regions. Furthermore, as we have shown recently [13], both single-and multiple-carrier mechanisms of bond dissociation provide substantial contributions to HCD. More importantly, contrary to the common perception, the multiple-carrier bond-breakage process appears to give a significant contribution also in nMOSFETs with gate lengths as long as 2 μm when stressed at high voltages [14]- [16].…”

“…ViennaMesh generates meshes based on the built-in potential ( Fig. 2) [13]. The resulting mesh has a fine resolution in important regions, a sufficiently low density in less important regions, and contains ∼11 000 elements.…”

“…This is computationally challenging and becomes even more challenging for LDMOS transistors. First, this is related to the typical dimensions of LDMOS devices, as compared with nanoscale CMOS transistors, and thus to a mesh that contains a large number of cells, i.e., ∼10 000 [13]. Second, these transistors have a sophisticated architecture, including the bird's beak and the nonplanar interface ( Fig.…”

Transformation invariant local element size specification

“…represented by scalar fields, has significant impact on the convergence behavior of numerical simulations such as the deterministic solution of the Boltzmann transport equation [23]. Especially in regions of high doping profile changes, a fine mesh resolution is of advantage for the simulation process.…”

“…A material-aware mesh generation process for a transistor device [23] is presented in Section 4.1. Section 4.2 covers a geometry optimization process taking advantage of both the element sizing framework as well as ViennaMesh's template-based geometry kernel.…”