Physics-based drain current modeling of gate-all-around junctionless nanowire twin-gate transistor (JN-TGT) for digital applications

Pratap, Yogesh; Gautam, Rajni; Haldar, Subhasis; Gupta, Radhey S.; Gupta, Mridula

doi:10.1007/s10825-016-0798-1

Cited by 11 publications

(5 citation statements)

References 20 publications

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“…A new type of structure with two and three gates is arranged on a nanowire in such a way that a new type of implementation of logic gates has been developed [75]. Pratap et al in their letter have implemented a logic gate as a digital application by using gate all around junctionless nanowire transistors with twin gates.…”

Section: Logic Gate Implementationmentioning

confidence: 99%

“…The two gates are independently controlled and are separated by a small dielectric region. The width of the dielectric is taken to be very small so that the region under the depletion area can easily get depleted by metal gates [75]. The work function of gate 1 is kept at a higher value than gate 2, such that the region that is near to the drain should get ON before the region that is near the source side.…”

Section: Logic Gate Implementationmentioning

confidence: 99%

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A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

Narula,

Agarwal,

Verma

2024

Eng. Res. Express

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The Short Channel Effects (SCE) are becoming more prominent in Complementary Metal Oxide Semiconductor (CMOS) circuits with an introduction of nanoscale Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The short channel effects (SCE’s) and fabrication challenges have provoked the researchers to think for some other technologies to enhance the market of semiconductor devices. To overcome these SCE’s, various methodologies such as multi-gate structures, material engineering, gate engineering, dielectric pockets, strain technology, high K dielectric material, heterostructures, source and drain extensions etc. have been implemented. However, at very short channel lengths, the sharp edges of doping are difficult to obtain and thus SCE’s have become so difficult to control even after the implementations of different methodologies. Therefore, a new type of technology has been introduced to overcome such pitfalls e.g. transistors without junctions. Junctionless field effect transistor (JLFET) is one of the technologies which has overcome various SCE’s. Although the research on various issues has been addressed by different authors but still there is an impediment in the commercialization of the same device. The different technology boosters have been incorporated into junctionless based devices to escalate the performance. The technology boosting aspect of junctionless FET has been reviewed in this paper which has not been considered yet. In this paper distinct technology boosters and numerous effects on junctionless devices have been studied and presented. The performance of the junctionless FET devices are studied on incorporating the different semiconductor materials, effect of strain, use of high k dielectric, use of dielectric pockets, effect of gate misalignment, use of heterostructures, silicon on nothing (SON), vertically stacked nanowires, newly proposed rectangular core-shell based junctionless FET’s and roles of various physical parameters such as temperature, nanowire widths and effect of scattering mechanism on the performance of JLFET have been addressed.

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Section: Logic Gate Implementationmentioning

confidence: 99%

Section: Logic Gate Implementationmentioning

confidence: 99%

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

Narula,

Agarwal,

Verma

2024

Eng. Res. Express

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“…If two gates are present, the structure is defined as a twin gate transistor (Figure 7). Such a structure allows implementing logic gates easily since two inputs are present [34]. The twin gate structure can also be applied to a double channel GAAFET, as shown in Figure 7b.…”

Section: Gate-all-aroundmentioning

confidence: 99%

“…This device turned out to be the first one of a new generation of transistors. In the last decades, many other junctionless devices were proposed, which includes FinFET , Gate-All-Around (GAA) [24][25][26][27][28][29][30][31][32][33][34][35][36][37], Single Gate (SGJLT) [38][39][40][41][42][43][44][45][46][47][48][49][50], Double Gate (DGJLT) , Thin Film (TFT) [76][77][78][79][80][81][82][83][84][85][86], and Tunnel FET (TFET) [87][88][89][90][91][92][93][94][95][96][97]. Because most of the review papers on JLTs were published in 2010-2014…”

Section: Introductionmentioning

confidence: 99%

Junctionless Transistors: State-of-the-Art

2020

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Recent advances in semiconductor technology provide us with the resources to explore alternative methods for fabricating transistors with the goal of further reducing their sizes to increase transistor density and enhance performance. Conventional transistors use semiconductor junctions; they are formed by doping atoms on the silicon substrate that makes p-type and n-type regions. Decreasing the size of such transistors means that the junctions will get closer, which becomes very challenging when the size is reduced to the lower end of the nanometer scale due to the requirement of extremely high gradients in doping concentration. One of the most promising solutions to overcome this issue is realizing junctionless transistors. The first junctionless device was fabricated in 2010 and, since then, many other transistors of this kind (such as FinFET, Gate-All-Around, Thin Film) have been proposed and investigated. All of these semiconductor devices are characterized by junctionless structures, but they differ from each other when considering the influence of technological parameters on their performance. The aim of this review paper is to provide a simple but complete analysis of junctionless transistors, which have been proposed in the last decade. In this work, junctionless transistors are classified based on their geometrical structures, analytical model, and electrical characteristics. Finally, we used figure of merits, such as I o n / I o f f , D I B L , and S S , to highlight the advantages and disadvantages of each junctionless transistor category.

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“…The study of channel engineered nanotubes can exhibit enhanced device performance by suppression of SCEs (Pratap, Y., Gautam, R., Haldar, S., Gupta, R.S. and Gupta, M., 2016, Baral, K., Singh, P.K., Kumar, S., Chander, S. and Jit, S., 2020& Sahay, S. and Kumar, M.J., 2016.…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis of Charge Plasma Induced Graded Channel Si Nanotube

Ashima

Vaithiyanathan²,

Raj³

2021

JER is an international, peer-reviewed journal that publishes f

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This paper investigates a comparison based on DC and AC analysis of a charge plasma-based graded channel nanotube in two configurations. Nanotube structures offer enhanced gate ctontrol over other devices, they offer higher on-current than nanowires of equivalent silicon film thickness, making them a promising device, however, the core gate of nanotube results in higher gate leakages also. This paper draws a comparison of the two possible configurations of making a graded channel without ion implantation. The results show that a gate of higher work function in S-GC-NTFET is necessary to bring the same subthreshold characteristics as D-GC-NTFET. The D configuration shows slightly enhanced DC characteristics however, the RF analysis shows better results for S configuration.

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Physics-based drain current modeling of gate-all-around junctionless nanowire twin-gate transistor (JN-TGT) for digital applications

Cited by 11 publications

References 20 publications

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

Junctionless Transistors: State-of-the-Art

Performance Analysis of Charge Plasma Induced Graded Channel Si Nanotube

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